Remove unwanted condition check for frame length adjustment.
For ZynqMP / Versal the ref clk is set to 20Mhz frequency and it is always
recommended. For 20Mhz frequency the refclk_fladj value should be 0, so
clear bits 21:8 in GFLADJ register.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
refclk_fladj = dev_read_bool(dev, "snps,refclk_fladj");
- if (refclk_fladj) {
- if ((reg & GFLADJ_REFCLK_FLADJ) != (fladj &
- GFLADJ_REFCLK_FLADJ)) {
- reg &= ~GFLADJ_REFCLK_FLADJ;
- reg |= (fladj & GFLADJ_REFCLK_FLADJ);
- }
- }
+ if (refclk_fladj)
+ reg &= ~GFLADJ_REFCLK_FLADJ;
if ((reg & GFLADJ_30MHZ_MASK) != fladj) {
reg &= ~GFLADJ_30MHZ_MASK;