drm/amd/pm: Add generic pcie dpm table

Add a generic pcie dpm table which contains the number of link clock
levels and link clock, pcie gen speed/width corresponding to each level.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 3d67d948eaff944128610d56c70946ce185c7ce0..a4e8e488030fad5b772f621c00eb350a1a74bf03 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -314,6 +314,15 @@ struct smu_dpm_table {
 #define SMU_DPM_TABLE_MAX(table) \
        ((table)->count > 0 ? (table)->dpm_levels[(table)->count - 1].value : 0)
 
+#define SMU_MAX_PCIE_LEVELS 3
+
+struct smu_pcie_table {
+       uint8_t pcie_gen[SMU_MAX_PCIE_LEVELS];
+       uint8_t pcie_lane[SMU_MAX_PCIE_LEVELS];
+       uint16_t lclk_freq[SMU_MAX_PCIE_LEVELS];
+       uint32_t lclk_levels;
+};
+
 struct smu_bios_boot_up_values {
        uint32_t                        revision;
        uint32_t                        gfxclk;