* config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
* config/arm/arm-protos.h (FL2_ARCH8_1): New.
(FL2_FOR_ARCH8_1A): New.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (arm_arch8_1): New.
(arm_option_override): Set arm_arch8_1.
* config/arm/arm.h (TARGET_NEON_RDMA): New.
(arm_arch8_1): Declare.
* doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
"armv8.1-a+crc".
(ARM Options, -mfpu): Fix a typo.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231678
138bc75d-0d04-0410-961f-
82ee72b054a4
+2015-12-16 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/arm/arm-arches.def: Add "armv8.1-a" and "armv8.1-a+crc".
+ * config/arm/arm-protos.h (FL2_ARCH8_1): New.
+ (FL2_FOR_ARCH8_1A): New.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm.c (arm_arch8_1): New.
+ (arm_option_override): Set arm_arch8_1.
+ * config/arm/arm.h (TARGET_NEON_RDMA): New.
+ (arm_arch8_1): Declare.
+ * doc/invoke.texi (ARM Options, -march): Add "armv8.1-a" and
+ "armv8.1-a+crc".
+ (ARM Options, -mfpu): Fix a typo.
+
2015-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/68648
ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7EM))
ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH8A))
ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A))
+ARM_ARCH ("armv8.1-a", cortexa53, 8A,
+ ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
+ARM_ARCH ("armv8.1-a+crc",cortexa53, 8A,
+ ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
+ FL2_FOR_ARCH8_1A))
ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
#define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */
+#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */
+
/* Flags that only effect tuning, not available instructions. */
#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
| FL_CO_PROC)
#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
+#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
/* There are too many feature bits to fit in a single word so the set of cpu and
fpu capabilities is a structure. A feature set is created and manipulated
Enum(arm_arch) String(armv8-a+crc) Value(26)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(27)
+Enum(arm_arch) String(armv8.1-a) Value(27)
EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(28)
+Enum(arm_arch) String(armv8.1-a+crc) Value(28)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt) Value(29)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(30)
Enum
Name(arm_fpu) Type(int)
/* Nonzero if instructions present in ARMv8 can be used. */
int arm_arch8 = 0;
+/* Nonzero if this chip supports the ARMv8.1 extensions. */
+int arm_arch8_1 = 0;
+
/* Nonzero if this chip can benefit from load scheduling. */
int arm_ld_sched = 0;
arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7);
arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+ arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
(TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \
&& ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
+/* FPU supports ARMv8.1 Adv.SIMD extensions. */
+#define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
+
/* Q-bit is present. */
#define TARGET_ARM_QBIT \
(TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
/* Nonzero if this chip supports the ARM Architecture 8 extensions. */
extern int arm_arch8;
+/* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */
+extern int arm_arch8_1;
+
/* Nonzero if this chip can benefit from load scheduling. */
extern int arm_ld_sched;
@samp{armv6}, @samp{armv6j},
@samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
-@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc},
-@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
+@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
@option{-march=armv7ve} is the armv7-a architecture with virtualization
extensions.
@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
@samp{fpv5-d16}, @samp{fpv5-sp-d16},
-@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}.
+@samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
If @option{-msoft-float} is specified this specifies the format of
floating-point values.