x86/cpu: Validate CPUID leaf 0x2 EDX output

commit 1881148215c67151b146450fb89ec22fd92337a7 upstream.

CPUID leaf 0x2 emits one-byte descriptors in its four output registers
EAX, EBX, ECX, and EDX.  For these descriptors to be valid, the most
significant bit (MSB) of each register must be clear.

Leaf 0x2 parsing at intel.c only validated the MSBs of EAX, EBX, and
ECX, but left EDX unchecked.

Validate EDX's most-significant bit as well.

Fixes: e0ba94f14f74 ("x86/tlb_info: get last level TLB entry number of CPU")
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: stable@kernel.org
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250304085152.51092-3-darwi@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 4b5f3d0521517aebc1acc506b00df85b7a9ce709..9c0cf41bf6171db3435d2f6026e3305283cd3bf3 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -836,7 +836,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
                cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
 
                /* If bit 31 is set, this is an unknown format */
-               for (j = 0 ; j < 3 ; j++)
+               for (j = 0 ; j < 4 ; j++)
                        if (regs[j] & (1 << 31))
                                regs[j] = 0;