]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: ath12k: handle REO status ring for QCC2072
authorBaochen Qiang <baochen.qiang@oss.qualcomm.com>
Mon, 12 Jan 2026 07:36:34 +0000 (15:36 +0800)
committerJeff Johnson <jeff.johnson@oss.qualcomm.com>
Fri, 16 Jan 2026 01:19:41 +0000 (17:19 -0800)
For QCC2072 below REO status descriptors are different compared with
QCN9274/WCN7850:

        hal_reo_get_queue_stats_status
        hal_reo_flush_queue_status
        hal_reo_flush_cache_status
        hal_reo_unblock_cache_status
        hal_reo_flush_timeout_list_status
        hal_reo_desc_thresh_reached_status

Take hal_reo_get_queue_stats_status as an example:

QCC2072:
struct hal_reo_get_queue_stats_status_qcc2072 {
        __le32 tlv32_padding;
        struct hal_reo_get_queue_stats_status status;
} __packed;

QCN9274/WCN7850:
struct hal_reo_get_queue_stats_status;

Besides, QCC2072 has a 32 bits TLV header while QCN9274/WCN7850 has 64.

This means that there is no difference between these 3 devices in layout
of actual fields, because they all start after a 8 bytes offset

QCC2072:
{
struct hal_tlv_hdr tlv;
__le32 tlv32_padding;
struct hal_reo_get_queue_stats_status status;
}

QCN9274/WCN7850:
{
struct hal_tlv_64_hdr tlv;
struct hal_reo_get_queue_stats_status status;
}

Therefore current implementation luckily works for QCC2072 as well.
However it leads to misunderstanding, which should be avoided.

So add individual REO status ring handling for QCC2072.

Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0-01560-QCACOLSWPL_V1_TO_SILICONZ-1
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3

Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260112-ath12k-support-qcc2072-v2-14-fc8ce1e43969@oss.qualcomm.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
drivers/net/wireless/ath/ath12k/hal.c
drivers/net/wireless/ath/ath12k/hal.h
drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h
drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c

index 5ce5e0f89ca885eb50b3a622e884793c4a5e2e6f..a164563fff289c3ac981d7222f3819b58bf6d910 100644 (file)
@@ -857,3 +857,15 @@ u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc)
        return tag;
 }
 EXPORT_SYMBOL(ath12k_hal_decode_tlv64_hdr);
+
+u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc)
+{
+       struct hal_tlv_hdr *tlv32 = tlv;
+       u16 tag;
+
+       tag = le32_get_bits(tlv32->tl, HAL_SRNG_TLV_HDR_TAG);
+       *desc = tlv32->value;
+
+       return tag;
+}
+EXPORT_SYMBOL(ath12k_hal_decode_tlv32_hdr);
index f322000e8ac9f3cd0667a969d87f3aac5f8fb48e..520587305dfa628b5c40c093a33f60b5a6a675ee 100644 (file)
@@ -1546,4 +1546,5 @@ void ath12k_hal_rx_reo_ent_buf_paddr_get(struct ath12k_hal *hal, void *rx_desc,
 void *ath12k_hal_encode_tlv64_hdr(void *tlv, u64 tag, u64 len);
 void *ath12k_hal_encode_tlv32_hdr(void *tlv, u64 tag, u64 len);
 u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc);
+u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc);
 #endif
index c4c7ca9ee827ac1e584049c7616eb85f19b257e9..e1ab47b44433dde633df5887032ce6e6e64ed42f 100644 (file)
@@ -2439,6 +2439,11 @@ struct hal_reo_get_queue_stats_status {
  *             entries into this Ring has looped around the ring.
  */
 
+struct hal_reo_get_queue_stats_status_qcc2072 {
+       __le32 tlv32_padding;
+       struct hal_reo_get_queue_stats_status status;
+} __packed;
+
 #define HAL_REO_STATUS_LOOP_CNT                        GENMASK(31, 28)
 
 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
index 0ae5b073287aba42b14214662af437941e2da795..ee2427fadfc141c328d733443e63b5e8112105e2 100644 (file)
@@ -425,9 +425,28 @@ static int ath12k_hal_srng_create_config_qcc2072(struct ath12k_hal *hal)
        s->entry_size = (sizeof(struct hal_tlv_hdr) +
                         sizeof(struct hal_reo_get_queue_stats_qcc2072)) >> 2;
 
+       s = &hal->srng_config[HAL_REO_STATUS];
+       s->entry_size = (sizeof(struct hal_tlv_hdr) +
+                        sizeof(struct hal_reo_get_queue_stats_status_qcc2072)) >> 2;
+
        return 0;
 }
 
+static u16 ath12k_hal_reo_status_dec_tlv_hdr_qcc2072(void *tlv, void **desc)
+{
+       struct hal_reo_get_queue_stats_status_qcc2072 *status_tlv;
+       u16 tag;
+
+       tag = ath12k_hal_decode_tlv32_hdr(tlv, (void **)&status_tlv);
+       /*
+        * actual desc of REO status entry starts after tlv32_padding,
+        * see hal_reo_get_queue_stats_status_qcc2072
+        */
+       *desc = &status_tlv->status;
+
+       return tag;
+}
+
 const struct hal_ops hal_qcc2072_ops = {
        .create_srng_config = ath12k_hal_srng_create_config_qcc2072,
        .rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_qcc2072,
@@ -468,7 +487,7 @@ const struct hal_ops hal_qcc2072_ops = {
        .rx_msdu_list_get = ath12k_wifi7_hal_rx_msdu_list_get,
        .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get,
        .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv32_hdr,
-       .reo_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr,
+       .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_qcc2072,
 };
 
 u32 ath12k_hal_rx_desc_get_mpdu_start_offset_qcc2072(void)