arm64: dts: imx8mm: Add Root Port node and PERST property

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 8be44eaf4e1e0adc2921db8cc5f2dc69586b68cf..e03aba825c18f8f7a26b9e4936603f0da86c3d44 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -533,6 +533,7 @@
 &pcie0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
        clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
                 <&clk IMX8MM_CLK_PCIE1_AUX>;
@@ -559,6 +560,10 @@
        status = "disabled";
 };
 
+&pcie0_port0 {
+       reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+};
+
 &sai2 {
        #sound-dai-cells = <0>;
        pinctrl-names = "default";

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 4cc5ad01d0e2c520d9b212c2658d7b1a233be506..5cf2998d396d930cc385433d1c5bc049c8042ba2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1370,6 +1370,17 @@
                        phys = <&pcie_phy>;
                        phy-names = "pcie-phy";
                        status = "disabled";
+
+                       pcie0_port0: pcie@0 {
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie0_ep: pcie-ep@33800000 {