]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings
authorGuoniu.zhou <guoniu.zhou@nxp.com>
Thu, 22 May 2025 17:56:47 +0000 (13:56 -0400)
committerHans Verkuil <hverkuil@xs4all.nl>
Wed, 18 Jun 2025 07:21:59 +0000 (09:21 +0200)
Introduce `imx8mq_plat_data` along with enable/disable callback operations
to facilitate support for new chips. No functional changes.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250522-8qxp_camera-v5-9-d4be869fdb7e@nxp.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
drivers/media/platform/nxp/imx8mq-mipi-csi2.c

index a8bcf60e2f37df6ff34add04124b60c3bc9933ed..59ec7107b4508dcce5d5ee71158bfcc11afbea0f 100644 (file)
@@ -62,6 +62,8 @@
 #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL       0x188
 #define CSI2RX_CFG_DISABLE_PAYLOAD_1           0x130
 
+struct csi_state;
+
 enum {
        ST_POWERED      = 1,
        ST_STREAMING    = 2,
@@ -83,11 +85,10 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
 
 #define CSI2_NUM_CLKS  ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
 
-#define        GPR_CSI2_1_RX_ENABLE            BIT(13)
-#define        GPR_CSI2_1_VID_INTFC_ENB        BIT(12)
-#define        GPR_CSI2_1_HSEL                 BIT(10)
-#define        GPR_CSI2_1_CONT_CLK_MODE        BIT(8)
-#define        GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
+struct imx8mq_plat_data {
+       int (*enable)(struct csi_state *state, u32 hs_settle);
+       void (*disable)(struct csi_state *state);
+};
 
 /*
  * The send level configures the number of entries that must accumulate in
@@ -106,6 +107,7 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
 
 struct csi_state {
        struct device *dev;
+       const struct imx8mq_plat_data *pdata;
        void __iomem *regs;
        struct clk_bulk_data clks[CSI2_NUM_CLKS];
        struct reset_control *rst;
@@ -137,6 +139,34 @@ struct csi2_pix_format {
        u8 width;
 };
 
+/* -----------------------------------------------------------------------------
+ * i.MX8MQ GPR
+ */
+
+#define        GPR_CSI2_1_RX_ENABLE            BIT(13)
+#define        GPR_CSI2_1_VID_INTFC_ENB        BIT(12)
+#define        GPR_CSI2_1_HSEL                 BIT(10)
+#define        GPR_CSI2_1_CONT_CLK_MODE        BIT(8)
+#define        GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
+
+static int imx8mq_gpr_enable(struct csi_state *state, u32 hs_settle)
+{
+       regmap_update_bits(state->phy_gpr,
+                          state->phy_gpr_reg,
+                          0x3fff,
+                          GPR_CSI2_1_RX_ENABLE |
+                          GPR_CSI2_1_VID_INTFC_ENB |
+                          GPR_CSI2_1_HSEL |
+                          GPR_CSI2_1_CONT_CLK_MODE |
+                          GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
+
+       return 0;
+}
+
+static const struct imx8mq_plat_data imx8mq_data = {
+       .enable = imx8mq_gpr_enable,
+};
+
 static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
        /* RAW (Bayer and greyscale) formats. */
        {
@@ -371,14 +401,9 @@ static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
        if (ret)
                return ret;
 
-       regmap_update_bits(state->phy_gpr,
-                          state->phy_gpr_reg,
-                          0x3fff,
-                          GPR_CSI2_1_RX_ENABLE |
-                          GPR_CSI2_1_VID_INTFC_ENB |
-                          GPR_CSI2_1_HSEL |
-                          GPR_CSI2_1_CONT_CLK_MODE |
-                          GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
+       ret = state->pdata->enable(state, hs_settle);
+       if (ret)
+               return ret;
 
        return 0;
 }
@@ -386,6 +411,9 @@ static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
 static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
 {
        imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
+
+       if (state->pdata->disable)
+               state->pdata->disable(state);
 }
 
 /* -----------------------------------------------------------------------------
@@ -876,6 +904,8 @@ static int imx8mq_mipi_csi_probe(struct platform_device *pdev)
 
        state->dev = dev;
 
+       state->pdata = of_device_get_match_data(dev);
+
        ret = imx8mq_mipi_csi_parse_dt(state);
        if (ret < 0) {
                dev_err(dev, "Failed to parse device tree: %d\n", ret);
@@ -953,7 +983,7 @@ static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
-       { .compatible = "fsl,imx8mq-mipi-csi2", },
+       { .compatible = "fsl,imx8mq-mipi-csi2", .data = &imx8mq_data },
        { /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);