]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
phy: exynos5-usbdrd: Add support for the Exynos990 usbdrd phy
authorIgor Belwon <igor.belwon@mentallysanemainliners.org>
Thu, 15 May 2025 14:43:02 +0000 (16:43 +0200)
committerVinod Koul <vkoul@kernel.org>
Sat, 14 Jun 2025 12:19:09 +0000 (17:49 +0530)
The Exynos990 usbdrd PHY is a combo PHY which supports USB SS, HS and
DisplayPort outputs. This commit adds support only for UTMI+ (USB HS).

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250515-usb-resends-may-15-v3-2-ad33a85b6cee@mentallysanemainliners.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/samsung/phy-exynos5-usbdrd.c
include/linux/soc/samsung/exynos-regs-pmu.h

index 917a76d584f0856f1e445630e2cf97b3c3e46b13..dd660ebe80458a13413ca9735339b4e1095af8ea 100644 (file)
@@ -2025,6 +2025,35 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
        .n_regulators           = ARRAY_SIZE(exynos5_regulator_names),
 };
 
+static const struct exynos5_usbdrd_phy_tuning exynos990_tunes_utmi_postinit[] = {
+       PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON,
+                            (HSPPARACON_TXVREF |
+                             HSPPARACON_TXPREEMPAMP | HSPPARACON_SQRX |
+                             HSPPARACON_COMPDIS),
+                            (FIELD_PREP_CONST(HSPPARACON_TXVREF, 7) |
+                             FIELD_PREP_CONST(HSPPARACON_TXPREEMPAMP, 3) |
+                             FIELD_PREP_CONST(HSPPARACON_SQRX, 5) |
+                             FIELD_PREP_CONST(HSPPARACON_COMPDIS, 7))),
+       PHY_TUNING_ENTRY_LAST
+};
+
+static const struct exynos5_usbdrd_phy_tuning *exynos990_tunes[PTS_MAX] = {
+       [PTS_UTMI_POSTINIT] = exynos990_tunes_utmi_postinit,
+};
+
+static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = {
+       .phy_cfg                = phy_cfg_exynos850,
+       .phy_ops                = &exynos850_usbdrd_phy_ops,
+       .phy_tunes              = exynos990_tunes,
+       .pmu_offset_usbdrd0_phy = EXYNOS990_PHY_CTRL_USB20,
+       .clk_names              = exynos5_clk_names,
+       .n_clks                 = ARRAY_SIZE(exynos5_clk_names),
+       .core_clk_names         = exynos5_core_clk_names,
+       .n_core_clks            = ARRAY_SIZE(exynos5_core_clk_names),
+       .regulator_names        = exynos5_regulator_names,
+       .n_regulators           = ARRAY_SIZE(exynos5_regulator_names),
+};
+
 static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
        {
                .id             = EXYNOS5_DRDPHY_UTMI,
@@ -2228,6 +2257,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
        }, {
                .compatible = "samsung,exynos850-usbdrd-phy",
                .data = &exynos850_usbdrd_phy
+       }, {
+               .compatible = "samsung,exynos990-usbdrd-phy",
+               .data = &exynos990_usbdrd_phy
        },
        { },
 };
index 1a2c0e0838f99821151661878f022f2129a0c19b..7754697e581077ec0fd60b63649728896ca145c9 100644 (file)
 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION                    (0x3268)
 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION              (0x32A8)
 
+/* For Exynos990 */
+#define EXYNOS990_PHY_CTRL_USB20                               (0x72C)
+
 /* For Tensor GS101 */
 /* PMU ALIVE */
 #define GS101_SYSIP_DAT0                                       (0x810)