arm: [MVE intrinsics] factorize vddup vidup

Factorize vddup and vidup so that they use the same parameterized
names.

This patch updates only the (define_insn
"@mve_<mve_insn>q_u<mode>_insn") patterns and does not bother with the
(define_expand "mve_vidupq_n_u<mode>") ones, because a subsequent
patch avoids using them.

2024-08-21  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/iterators.md (mve_insn): Add VIDUPQ, VDDUPQ,
	VIDUPQ_M, VDDUPQ_M.
	(viddupq_op): New.
	(viddupq_m_op): New.
	(VIDDUPQ): New.
	(VIDDUPQ_M): New.
	* config/arm/mve.md (mve_vddupq_u<mode>_insn)
	(mve_vidupq_u<mode>_insn): Merge into ...
	(mve_<mve_insn>q_u<mode>_insn): ... this.
	(mve_vddupq_m_wb_u<mode>_insn, mve_vidupq_m_wb_u<mode>_insn):
	Merge into ...
	(mve_<mve_insn>q_m_wb_u<mode>_insn): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 3a1825ebab2e2426d289cd55cf40f7a21c0b0b90..c0299117f26e1cca69053ea56b39c2b8d41a4a4a 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1007,6 +1007,8 @@
                 (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
                 (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
                 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
+                (VIDUPQ "vidup") (VDDUPQ "vddup")
+                (VIDUPQ_M "vidup") (VDDUPQ_M "vddup")
                 (VMAXAQ_M_S "vmaxa")
                 (VMAXAQ_S "vmaxa")
                 (VMAXAVQ_P_S "vmaxav")
@@ -1340,6 +1342,9 @@
                 (VRNDXQ_F "vrintx") (VRNDXQ_M_F "vrintx")
                 ])
 
+(define_int_attr viddupq_op [ (VIDUPQ "plus") (VDDUPQ "minus")])
+(define_int_attr viddupq_m_op [ (VIDUPQ_M "plus") (VDDUPQ_M "minus")])
+
 ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
 ;; a stack pointer operand.  The minus operation is a candidate for an rsub
 ;; and hence only plus is supported.
@@ -2961,6 +2966,8 @@
 (define_int_iterator VCVTxQ_M_F32_F16 [VCVTBQ_M_F32_F16 VCVTTQ_M_F32_F16])
 (define_int_iterator VCVTxQ [VCVTAQ_S VCVTAQ_U VCVTMQ_S VCVTMQ_U VCVTNQ_S VCVTNQ_U VCVTPQ_S VCVTPQ_U])
 (define_int_iterator VCVTxQ_M [VCVTAQ_M_S VCVTAQ_M_U VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S VCVTNQ_M_U VCVTPQ_M_S VCVTPQ_M_U])
+(define_int_iterator VIDDUPQ [VIDUPQ VDDUPQ])
+(define_int_iterator VIDDUPQ_M [VIDUPQ_M VDDUPQ_M])
 (define_int_iterator DLSTP [DLSTP8 DLSTP16 DLSTP32
                                   DLSTP64])
 (define_int_iterator LETP [LETP8 LETP16 LETP32

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index cef55e8c9303ed5a2a152f35d6556c58fc11057b..d6022276240e2b681b54331612e5856641f64317 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -5078,18 +5078,18 @@
 })
 
 ;;
-;; [vidupq_u_insn])
+;; [vddupq_u_insn, vidupq_u_insn]
 ;;
-(define_insn "mve_vidupq_u<mode>_insn"
+(define_insn "@mve_<mve_insn>q_u<mode>_insn"
  [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
        (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
                      (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
-        VIDUPQ))
+       VIDDUPQ))
   (set (match_operand:SI 1 "s_register_operand" "=Te")
-       (plus:SI (match_dup 2)
-               (match_operand:SI 4 "immediate_operand" "i")))]
+       (<viddupq_op>:SI (match_dup 2)
+                       (match_operand:SI 4 "immediate_operand" "i")))]
  "TARGET_HAVE_MVE"
- "vidup.u%#<V_sz_elem>\t%q0, %1, %3")
+ "<mve_insn>.u%#<V_sz_elem>\t%q0, %1, %3")
 
 ;;
 ;; [vidupq_m_n_u])
@@ -5112,21 +5112,21 @@
 })
 
 ;;
-;; [vidupq_m_wb_u_insn])
+;; [vddupq_m_wb_u_insn, vidupq_m_wb_u_insn]
 ;;
-(define_insn "mve_vidupq_m_wb_u<mode>_insn"
+(define_insn "@mve_<mve_insn>q_m_wb_u<mode>_insn"
  [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
                      (match_operand:SI 3 "s_register_operand" "2")
                      (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
                      (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")]
-       VIDUPQ_M))
+       VIDDUPQ_M))
   (set (match_operand:SI 2 "s_register_operand" "=Te")
-       (plus:SI (match_dup 3)
-               (match_operand:SI 6 "immediate_operand" "i")))]
+       (<viddupq_m_op>:SI (match_dup 3)
+                         (match_operand:SI 6 "immediate_operand" "i")))]
  "TARGET_HAVE_MVE"
- "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vidupq_u<mode>_insn"))
+ "vpst\;<mve_insn>t.u%#<V_sz_elem>\t%q0, %2, %4"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_u<mode>_insn"))
   (set_attr "length""8")])
 
 ;;
@@ -5146,20 +5146,6 @@
   DONE;
 })
 
-;;
-;; [vddupq_u_insn])
-;;
-(define_insn "mve_vddupq_u<mode>_insn"
- [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
-       (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
-                     (match_operand:SI 3 "immediate_operand" "i")]
-       VDDUPQ))
-  (set (match_operand:SI 1 "s_register_operand" "=Te")
-       (minus:SI (match_dup 2)
-                (match_operand:SI 4 "immediate_operand" "i")))]
- "TARGET_HAVE_MVE"
- "vddup.u%#<V_sz_elem>\t%q0, %1, %3")
-
 ;;
 ;; [vddupq_m_n_u])
 ;;
@@ -5180,24 +5166,6 @@
   DONE;
 })
 
-;;
-;; [vddupq_m_wb_u_insn])
-;;
-(define_insn "mve_vddupq_m_wb_u<mode>_insn"
- [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
-       (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-                     (match_operand:SI 3 "s_register_operand" "2")
-                     (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
-                     (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")]
-       VDDUPQ_M))
-  (set (match_operand:SI 2 "s_register_operand" "=Te")
-       (minus:SI (match_dup 3)
-                (match_operand:SI 6 "immediate_operand" "i")))]
- "TARGET_HAVE_MVE"
- "vpst\;vddupt.u%#<V_sz_elem>\t%q0, %2, %4"
- [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vddupq_u<mode>_insn"))
-  (set_attr "length""8")])
-
 ;;
 ;; [vdwdupq_n_u])
 ;;