backport: re PR target/81375 (unrecognizable insn)

	Backport from mainline
	2017-07-10  Uros Bizjak  <ubizjak@gmail.com>

	PR target/81375
	* config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
	(rcpps): Ditto.
	(*rsqrtsf2_sse): Ditto.
	(rsqrtsf2): Ditto.
	(div<mode>3): Macroize insn from divdf3 and divsf3
	using MODEF mode iterator.

	Backport from mainline
	2017-07-04  Uros Bizjak  <ubizjak@gmail.com>

	PR target/81300
	* config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes):
	Require dead FLAGS_REG at the beginning of a peephole.

testsuite/ChangeLog:

	Backport from mainline
	2017-07-10  Uros Bizjak  <ubizjak@gmail.com>

	PR target/81375
	* gcc.target/i386/pr81375.c: New test.

	Backport from mainline
	2017-07-04  Uros Bizjak  <ubizjak@gmail.com>

	PR target/81300
	* gcc.target/i386/pr81300.c: New test.

From-SVN: r250211

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0e0af0df55007c260b8bdae5e8869076b3359ddd..d9437b99ff4f5dd575844e595b1b8f8cc143aa70 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+2017-07-14  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2017-07-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/81375
+       * config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
+       (rcpps): Ditto.
+       (*rsqrtsf2_sse): Ditto.
+       (rsqrtsf2): Ditto.
+       (div<mode>3): Macroize insn from divdf3 and divsf3
+       using MODEF mode iterator.
+
+       Backport from mainline
+       2017-07-04  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/81300
+       * config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes):
+       Require dead FLAGS_REG at the beginning of a peephole.
+
 2017-07-03  Tom de Vries  <tom@codesourcery.com>
 
        backport from mainline:

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f951e30e03d96eebf0dadac3f1dac076e6b0659c..ae4cc0775cecabddb0933c7cbecae5ea33a2cea5 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5159,7 +5159,7 @@
 (define_expand "floatunsdisf2"
   [(use (match_operand:SF 0 "register_operand"))
    (use (match_operand:DI 1 "nonimmediate_operand"))]
-  "TARGET_64BIT && TARGET_SSE_MATH"
+  "TARGET_64BIT && TARGET_SSE && TARGET_SSE_MATH"
   "x86_emit_floatuns (operands); DONE;")
 
 (define_expand "floatunsdidf2"
@@ -7107,21 +7107,15 @@
                (match_operand:XF 2 "register_operand")))]
   "TARGET_80387")
 
-(define_expand "divdf3"
-  [(set (match_operand:DF 0 "register_operand")
-       (div:DF (match_operand:DF 1 "register_operand")
-               (match_operand:DF 2 "nonimmediate_operand")))]
-   "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
-    || (TARGET_SSE2 && TARGET_SSE_MATH)")
-
-(define_expand "divsf3"
-  [(set (match_operand:SF 0 "register_operand")
-       (div:SF (match_operand:SF 1 "register_operand")
-               (match_operand:SF 2 "nonimmediate_operand")))]
-  "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
-    || TARGET_SSE_MATH"
+(define_expand "div<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand")
+       (div:MODEF (match_operand:MODEF 1 "register_operand")
+                  (match_operand:MODEF 2 "nonimmediate_operand")))]
+  "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
 {
-  if (TARGET_SSE_MATH
+  if (<MODE>mode == SFmode
+      && TARGET_SSE && TARGET_SSE_MATH
       && TARGET_RECIP_DIV
       && optimize_insn_for_speed_p ()
       && flag_finite_math_only && !flag_trapping_math
@@ -11657,7 +11651,8 @@
        (zero_extend (match_dup 1)))]
   "(peep2_reg_dead_p (3, operands[1])
     || operands_match_p (operands[1], operands[3]))
-   && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+   && ! reg_overlap_mentioned_p (operands[3], operands[0])
+   && peep2_regno_dead_p (0, FLAGS_REG)"
   [(set (match_dup 4) (match_dup 0))
    (set (strict_low_part (match_dup 5))
        (match_dup 2))]
@@ -11678,7 +11673,8 @@
   "(peep2_reg_dead_p (3, operands[1])
     || operands_match_p (operands[1], operands[3]))
    && ! reg_overlap_mentioned_p (operands[3], operands[0])
-   && ! reg_set_p (operands[3], operands[4])"
+   && ! reg_set_p (operands[3], operands[4])
+   && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (match_dup 5) (match_dup 0))
              (match_dup 4)])
    (set (strict_low_part (match_dup 6))
@@ -11700,7 +11696,8 @@
                   (and:SI (match_dup 3) (const_int 255)))
              (clobber (reg:CC FLAGS_REG))])]
   "REGNO (operands[1]) == REGNO (operands[3])
-   && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+   && ! reg_overlap_mentioned_p (operands[3], operands[0])
+   && peep2_regno_dead_p (0, FLAGS_REG)"
   [(set (match_dup 4) (match_dup 0))
    (set (strict_low_part (match_dup 5))
        (match_dup 2))]
@@ -11722,7 +11719,8 @@
   "(peep2_reg_dead_p (3, operands[1])
     || operands_match_p (operands[1], operands[3]))
    && ! reg_overlap_mentioned_p (operands[3], operands[0])
-   && ! reg_set_p (operands[3], operands[4])"
+   && ! reg_set_p (operands[3], operands[4])
+   && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (match_dup 5) (match_dup 0))
              (match_dup 4)])
    (set (strict_low_part (match_dup 6))
@@ -13778,7 +13776,7 @@
   [(set (match_operand:SF 0 "register_operand" "=x")
        (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
                   UNSPEC_RCP))]
-  "TARGET_SSE_MATH"
+  "TARGET_SSE && TARGET_SSE_MATH"
   "%vrcpss\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
@@ -14087,7 +14085,7 @@
   [(set (match_operand:SF 0 "register_operand" "=x")
        (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
                   UNSPEC_RSQRT))]
-  "TARGET_SSE_MATH"
+  "TARGET_SSE && TARGET_SSE_MATH"
   "%vrsqrtss\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
@@ -14099,7 +14097,7 @@
   [(set (match_operand:SF 0 "register_operand")
        (unspec:SF [(match_operand:SF 1 "nonimmediate_operand")]
                   UNSPEC_RSQRT))]
-  "TARGET_SSE_MATH"
+  "TARGET_SSE && TARGET_SSE_MATH"
 {
   ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
   DONE;
@@ -14128,7 +14126,7 @@
    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
 {
   if (<MODE>mode == SFmode
-      && TARGET_SSE_MATH
+      && TARGET_SSE && TARGET_SSE_MATH
       && TARGET_RECIP_SQRT
       && !optimize_function_for_size_p (cfun)
       && flag_finite_math_only && !flag_trapping_math

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 883b0106cdc661ca9f2588cee46c685dee0739e0..e0345251cb26f3e1a2a065728d36fec7b9a43f7d 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2017-07-14  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2017-07-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/81375
+       * gcc.target/i386/pr81375.c: New test.
+
+       Backport from mainline
+       2017-07-04  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/81300
+       * gcc.target/i386/pr81300.c: New test.
+
 2017-07-03  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
        * gcc.target/arm/fpscr.c: Require arm_vfp_ok instead of arm_fp_ok and

diff --git a/gcc/testsuite/gcc.target/i386/pr81300.c b/gcc/testsuite/gcc.target/i386/pr81300.c
new file mode 100644 (file)
index 0000000..11eb55f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr81300.c
@@ -0,0 +1,30 @@
+/* PR target/81300 */
+/* { dg-do run { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+int
+__attribute__((noinline, noclone))
+foo (void)
+{
+  unsigned long long _discard = 0, zero = 0, maxull = 0;
+  unsigned char zero1 = __builtin_ia32_addcarryx_u64 (0, 0, 0, &_discard);
+  unsigned char zero2 = __builtin_ia32_addcarryx_u64 (zero1, 0, 0, &zero);
+  __builtin_ia32_sbb_u64 (0x0, 2, -1, &_discard);
+  unsigned char one = __builtin_ia32_sbb_u64 (0, zero, 1, &maxull);
+  unsigned long long x = __builtin_ia32_sbb_u64 (one, zero2, 0, &_discard);
+
+  unsigned long long z1 = 0;
+  __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z1) : "r" (x));
+  unsigned long long z2 = 3;
+  __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z2) : "r" (x));
+
+  return 1 - (z1 | z2);
+}
+
+int main ()
+{
+  if (foo ())
+    __builtin_abort ();
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr81375.c b/gcc/testsuite/gcc.target/i386/pr81375.c
new file mode 100644 (file)
index 0000000..3930e9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr81375.c
@@ -0,0 +1,10 @@
+/* PR target/81375 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-80387 -mno-sse -mfpmath=sse" } */
+
+/* { dg-warning "SSE instruction set disabled, using 387 arithmetics" "" { target *-*-* } 0 } */
+
+float foo (float a, float b)
+{
+  return a / b;
+}