(match_operand:GPI 1 "memory_operand" ""))
(set (match_operand:GPI 2 "register_operand" "")
(match_operand:GPI 3 "memory_operand" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, true, <MODE>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, true)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, true);
(match_operand:GPI 1 "aarch64_reg_or_zero" ""))
(set (match_operand:GPI 2 "memory_operand" "")
(match_operand:GPI 3 "aarch64_reg_or_zero" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, false, <MODE>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, false)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, false);
(match_operand:GPF 1 "memory_operand" ""))
(set (match_operand:GPF 2 "register_operand" "")
(match_operand:GPF 3 "memory_operand" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, true, <MODE>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, true)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, true);
(match_operand:GPF 1 "aarch64_reg_or_fp_zero" ""))
(set (match_operand:GPF 2 "memory_operand" "")
(match_operand:GPF 3 "aarch64_reg_or_fp_zero" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, false, <MODE>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, false)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, false);
(match_operand:DREG 1 "memory_operand" ""))
(set (match_operand:DREG2 2 "register_operand" "")
(match_operand:DREG2 3 "memory_operand" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, true, <DREG:MODE>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, true)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, true);
(match_operand:DREG 1 "register_operand" ""))
(set (match_operand:DREG2 2 "memory_operand" "")
(match_operand:DREG2 3 "register_operand" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, false, <DREG:MODE>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, false)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, false);
(set (match_operand:VQ2 2 "register_operand" "")
(match_operand:VQ2 3 "memory_operand" ""))]
"TARGET_FLOAT
- && aarch64_operands_ok_for_ldpstp (operands, true, <VQ:MODE>mode)
+ && aarch64_operands_ok_for_ldpstp (operands, true)
&& (aarch64_tune_params.extra_tuning_flags
& AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS) == 0"
[(const_int 0)]
(set (match_operand:VQ2 2 "memory_operand" "")
(match_operand:VQ2 3 "register_operand" ""))]
"TARGET_FLOAT
- && aarch64_operands_ok_for_ldpstp (operands, false, <VQ:MODE>mode)
+ && aarch64_operands_ok_for_ldpstp (operands, false)
&& (aarch64_tune_params.extra_tuning_flags
& AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS) == 0"
[(const_int 0)]
(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
(set (match_operand:DI 2 "register_operand" "")
(sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
- "aarch64_operands_ok_for_ldpstp (operands, true, SImode)"
+ "aarch64_operands_ok_for_ldpstp (operands, true)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, true, SIGN_EXTEND);
(zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
(set (match_operand:DI 2 "register_operand" "")
(zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
- "aarch64_operands_ok_for_ldpstp (operands, true, SImode)"
+ "aarch64_operands_ok_for_ldpstp (operands, true)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, true, ZERO_EXTEND);
(match_operand:DSX 1 "aarch64_reg_zero_or_fp_zero" ""))
(set (match_operand:<FCVT_TARGET> 2 "memory_operand" "")
(match_operand:<FCVT_TARGET> 3 "aarch64_reg_zero_or_fp_zero" ""))]
- "aarch64_operands_ok_for_ldpstp (operands, false, <V_INT_EQUIV>mode)"
+ "aarch64_operands_ok_for_ldpstp (operands, false)"
[(const_int 0)]
{
aarch64_finish_ldpstp_peephole (operands, false);
}
/* Given OPERANDS of consecutive load/store, check if we can merge
- them into ldp/stp. LOAD is true if they are load instructions.
- MODE is the mode of memory operands. */
+ them into ldp/stp. LOAD is true if they are load instructions. */
bool
-aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
- machine_mode mode)
+aarch64_operands_ok_for_ldpstp (rtx *operands, bool load)
{
enum reg_class rclass_1, rclass_2;
rtx mem_1, mem_2, reg_1, reg_2;
if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2))
return false;
- /* Check if mem_1 is ok with the ldp-stp policy model. */
- if (!aarch64_mem_ok_with_ldpstp_policy_model (mem_1, load, mode))
- return false;
-
/* Check if the addresses are in the form of [base+offset]. */
bool reversed = false;
if (!aarch64_check_consecutive_mems (&mem_1, &mem_2, &reversed))
/* The lower memory access must be a mem-pair operand. */
rtx lower_mem = reversed ? mem_2 : mem_1;
- if (!aarch64_mem_pair_operand (lower_mem, GET_MODE (lower_mem)))
+ machine_mode lower_mem_mode = GET_MODE (lower_mem);
+ if (!aarch64_mem_pair_operand (lower_mem, lower_mem_mode))
+ return false;
+
+ /* Check if lower_mem is ok with the ldp-stp policy model. */
+ if (!aarch64_mem_ok_with_ldpstp_policy_model (lower_mem, load,
+ lower_mem_mode))
return false;
if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))