clk: renesas: Use bitfield helpers

Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const
respective non-const bitfields, instead of open-coding the same
operations.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>

diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 3abd6e5400aded6aadead32a56f3a061dfc0ac68..f7b827b5e9b2dd325f1e13b3736d72fc92159560 100644 (file)
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -7,6 +7,7 @@
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk-provider.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
        if (clock->src_mask == 0)
                return 0;
 
-       hw_index = (readl(clock->reg) & clock->src_mask) >>
-                  __ffs(clock->src_mask);
+       hw_index = field_get(clock->src_mask, readl(clock->reg));
        for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
                if (clock->parents[i] == hw_index)
                        return i;
@@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
        if (index >= clk_hw_get_num_parents(hw))
                return -EINVAL;
 
-       src = clock->parents[index] << __ffs(clock->src_mask);
+       src = field_prep(clock->src_mask, clock->parents[index]);
        writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);
        return 0;
 }

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 10ae20489df9abd8218ef4a41df9c2278b0b3db0..b954278ddd9d8aa86305a3b5393573ed907a4c59 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
 {
        struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
        unsigned int mult;
-       u32 val;
 
-       val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
-       mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;
+       mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1;
 
        return parent_rate * mult * pll_clk->fixed_mult;
 }
@@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 
        val = readl(pll_clk->pllcr_reg);
        val &= ~CPG_PLLnCR_STC_MASK;
-       val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
+       val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1);
        writel(val, pll_clk->pllcr_reg);
 
        for (i = 1000; i; i--) {
@@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
                                           unsigned long parent_rate)
 {
        struct cpg_z_clk *zclk = to_z_clk(hw);
-       unsigned int mult;
-       u32 val;
-
-       val = readl(zclk->reg) & zclk->mask;
-       mult = 32 - (val >> __ffs(zclk->mask));
+       unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));
 
        return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
                                     32 * zclk->fixed_div);
@@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
        if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
                return -EBUSY;
 
-       cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
+       cpg_reg_modify(zclk->reg, zclk->mask,
+                      field_prep(zclk->mask, 32 - mult));
 
        /*
         * Set KICK bit in FRQCRB to update hardware setting and wait for

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index fb9a876aaba5cbcd5dff30bb47486e06cb907cd0..db3a0b8ef2b936bb848cda48ec0c0cb97b20d546 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -279,11 +279,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
                                           unsigned long parent_rate)
 {
        struct cpg_z_clk *zclk = to_z_clk(hw);
-       unsigned int mult;
-       u32 val;
-
-       val = readl(zclk->reg) & zclk->mask;
-       mult = 32 - (val >> __ffs(zclk->mask));
+       unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));
 
        return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
                                     32 * zclk->fixed_div);
@@ -334,7 +330,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
        if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
                return -EBUSY;
 
-       cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
+       cpg_reg_modify(zclk->reg, zclk->mask,
+                      field_prep(zclk->mask, 32 - mult));
 
        /*
         * Set KICK bit in FRQCRB to update hardware setting and wait for