drm/amd/display: Restore full update for tiling change to linear

[Why]
There was previously a dc debug flag to indicate that tiling
changes should only be a medium update instead of full. The
function get_plane_info_type was refactored to not rely on dc
state, but in the process the logic was unintentionally changed,
which leads to screen corruption in some cases.

[How]
 - add flag to tiling struct to avoid full update when necessary

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1c57bfd1fd2d8e51dff92353ddf865d9e326d41a..7dac3f35f0e8f4d85804a651dadc35d80fca5820 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2769,28 +2769,12 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct
 
        if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) {
                update_flags->bits.swizzle_change = 1;
-               elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
 
-               switch (tiling->gfxversion) {
-               case DcGfxVersion9:
-               case DcGfxVersion10:
-               case DcGfxVersion11:
-                       if (tiling->gfx9.swizzle != DC_SW_LINEAR) {
-                               update_flags->bits.bandwidth_change = 1;
-                               elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
-                       }
-                       break;
-               case DcGfxAddr3:
-                       if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) {
-                               update_flags->bits.bandwidth_change = 1;
-                               elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
-                       }
-                       break;
-               case DcGfxVersion7:
-               case DcGfxVersion8:
-               case DcGfxVersionUnknown:
-               default:
-                       break;
+               if (tiling->flags.avoid_full_update_on_tiling_change) {
+                       elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
+               } else {
+                       update_flags->bits.bandwidth_change = 1;
+                       elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 9bf853edc46fc237705ed30a03aa8d34ebd96950..595e082db281617d6bac219406aff4b36c4ffbfe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -445,6 +445,10 @@ enum dc_gfxversion {
                        enum swizzle_mode_addr3_values swizzle;
                } gfx_addr3;/*gfx with addr3 and above*/
        };
+
+       struct {
+               bool avoid_full_update_on_tiling_change;
+       } flags;
 };
 
 /* Rotation angle */