if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
req->mode != MTD_OPS_RAW)
- rdesc->info.op_tmpl.data.ecc = true;
+ rdesc->info.op_tmpl->data.ecc = true;
else
- rdesc->info.op_tmpl.data.ecc = false;
+ rdesc->info.op_tmpl->data.ecc = false;
if (spinand->flags & SPINAND_HAS_READ_PLANE_SELECT_BIT)
column |= req->pos.plane << fls(nanddev_page_size(nand));
if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
req->mode != MTD_OPS_RAW)
- wdesc->info.op_tmpl.data.ecc = true;
+ wdesc->info.op_tmpl->data.ecc = true;
else
- wdesc->info.op_tmpl.data.ecc = false;
+ wdesc->info.op_tmpl->data.ecc = false;
if (spinand->flags & SPINAND_HAS_PROG_PLANE_SELECT_BIT)
column |= req->pos.plane << fls(nanddev_page_size(nand));
/* Write descriptor */
info.length = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
- info.op_tmpl.data.ecc = enable_ecc;
+ info.primary_op_tmpl = *spinand->op_templates->update_cache;
+ info.primary_op_tmpl.data.ecc = enable_ecc;
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
spinand->spimem, &info);
if (IS_ERR(desc))
spinand->dirmaps[plane].wdesc = desc;
/* Read descriptor */
- info.op_tmpl = *spinand->op_templates->read_cache;
- info.op_tmpl.data.ecc = enable_ecc;
+ info.primary_op_tmpl = *spinand->op_templates->read_cache;
+ info.primary_op_tmpl.data.ecc = enable_ecc;
desc = spinand_create_rdesc(spinand, &info);
if (IS_ERR(desc))
return PTR_ERR(desc);
static int spi_nor_create_read_dirmap(struct spi_nor *nor)
{
struct spi_mem_dirmap_info info = {
- .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
- SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
- SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
- SPI_MEM_OP_DATA_IN(0, NULL, 0)),
+ .op_tmpl = &info.primary_op_tmpl,
+ .primary_op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
+ SPI_MEM_OP_DATA_IN(0, NULL, 0)),
.offset = 0,
.length = nor->params->size,
};
- struct spi_mem_op *op = &info.op_tmpl;
+ struct spi_mem_op *op = info.op_tmpl;
spi_nor_spimem_setup_op(nor, op, nor->read_proto);
static int spi_nor_create_write_dirmap(struct spi_nor *nor)
{
struct spi_mem_dirmap_info info = {
- .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
- SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
+ .op_tmpl = &info.primary_op_tmpl,
+ .primary_op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
.offset = 0,
.length = nor->params->size,
};
- struct spi_mem_op *op = &info.op_tmpl;
+ struct spi_mem_op *op = info.op_tmpl;
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op->addr.nbytes = 0;
if (desc->info.length > SPI_NAND_CACHE_SIZE)
return -E2BIG;
- if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!airoha_snand_supports_op(desc->mem, desc->info.op_tmpl))
return -EOPNOTSUPP;
return 0;
* DUALIO and QUADIO opcodes are not supported by the spi controller,
* replace them with supported opcodes.
*/
- opcode = desc->info.op_tmpl.cmd.opcode;
+ opcode = desc->info.op_tmpl->cmd.opcode;
switch (opcode) {
case SPI_NAND_OP_READ_FROM_CACHE_SINGLE:
case SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST:
/* minimum oob size is 64 */
bytes = round_up(offs + len, 64);
- opcode = desc->info.op_tmpl.cmd.opcode;
+ opcode = desc->info.op_tmpl->cmd.opcode;
switch (opcode) {
case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
case SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE:
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
- struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct spi_mem_op *op = desc->info.op_tmpl;
u32 ctl_val;
int ret = 0;
if (chip->ahb_window_size < offset + len || chip->force_user_mode) {
int ret;
- ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
+ ret = aspeed_spi_read_user(chip, desc->info.op_tmpl, offset, len, buf);
if (ret < 0)
return ret;
} else {
struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
const struct intel_spi_mem_op *iop;
- iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);
+ iop = intel_spi_match_mem_op(ispi, desc->info.op_tmpl);
if (!iop)
return -EOPNOTSUPP;
{
struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
const struct intel_spi_mem_op *iop = desc->priv;
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
/* Fill in the gaps */
{
struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
const struct intel_spi_mem_op *iop = desc->priv;
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
op.addr.val = offs;
static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
op.addr.val = desc->info.offset + offs;
static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, const void *buf)
{
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
op.addr.val = desc->info.offset + offs;
int ret = -ENOTSUPP;
/* Make sure the number of address cycles is between 1 and 8 bytes. */
- if (!info->op_tmpl.addr.nbytes || info->op_tmpl.addr.nbytes > 8)
+ if (!info->primary_op_tmpl.addr.nbytes || info->primary_op_tmpl.addr.nbytes > 8)
return ERR_PTR(-EINVAL);
/* data.dir should either be SPI_MEM_DATA_IN or SPI_MEM_DATA_OUT. */
- if (info->op_tmpl.data.dir == SPI_MEM_NO_DATA)
+ if (info->primary_op_tmpl.data.dir == SPI_MEM_NO_DATA)
return ERR_PTR(-EINVAL);
desc = kzalloc_obj(*desc);
desc->mem = mem;
desc->info = *info;
+ desc->info.op_tmpl = &desc->info.primary_op_tmpl;
if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create) {
ret = spi_mem_access_start(mem);
if (ret) {
if (ret) {
desc->nodirmap = true;
- if (!spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!spi_mem_supports_op(desc->mem, &desc->info.primary_op_tmpl))
ret = -EOPNOTSUPP;
else
ret = 0;
struct spi_controller *ctlr = desc->mem->spi->controller;
ssize_t ret;
- if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
+ if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
return -EINVAL;
if (!len)
struct spi_controller *ctlr = desc->mem->spi->controller;
ssize_t ret;
- if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_OUT)
+ if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_OUT)
return -EINVAL;
if (!len)
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
return -EINVAL;
- writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+ writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl->data.swap16),
mxic->regs + HC_CFG);
- writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
+ writel(mxic_spi_mem_prep_op_cfg(desc->info.op_tmpl, len),
mxic->regs + LRD_CFG);
writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LRD_RANGE);
- writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ writel(LMODE_CMD0(desc->info.op_tmpl->cmd.opcode) |
LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |
LMODE_EN,
mxic->regs + LRD_CTRL);
- if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
+ if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl->data.ecc) {
ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
NAND_PAGE_READ,
mxic->linear.dma + offs);
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
return -EINVAL;
- writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+ writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl->data.swap16),
mxic->regs + HC_CFG);
- writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
+ writel(mxic_spi_mem_prep_op_cfg(desc->info.op_tmpl, len),
mxic->regs + LWR_CFG);
writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LWR_RANGE);
- writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ writel(LMODE_CMD0(desc->info.op_tmpl->cmd.opcode) |
LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |
LMODE_EN,
mxic->regs + LWR_CTRL);
- if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
+ if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl->data.ecc) {
ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
NAND_PAGE_WRITE,
mxic->linear.dma + offs);
if (desc->info.offset + desc->info.length > U32_MAX)
return -EINVAL;
- if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!mxic_spi_mem_supports_op(desc->mem, desc->info.op_tmpl))
return -EOPNOTSUPP;
return 0;
for (i = 0 ; i < len ; i++)
*(buf_rx + i) = ioread8(src + i);
} else {
- if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||
- desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||
- desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||
- desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)
- npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
+ if (desc->info.op_tmpl->addr.buswidth != fiu->drd_op.addr.buswidth ||
+ desc->info.op_tmpl->dummy.nbytes != fiu->drd_op.dummy.nbytes ||
+ desc->info.op_tmpl->cmd.opcode != fiu->drd_op.cmd.opcode ||
+ desc->info.op_tmpl->addr.nbytes != fiu->drd_op.addr.nbytes)
+ npcm_fiu_set_drd(fiu, desc->info.op_tmpl);
memcpy_fromio(buf_rx, src, len);
}
}
if (!fiu->spix_mode &&
- desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
+ desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT) {
desc->nodirmap = true;
return 0;
}
NPCM_FIU_CFG_FIU_FIX);
}
- if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
+ if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN) {
if (!fiu->spix_mode)
- npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
+ npcm_fiu_set_drd(fiu, desc->info.op_tmpl);
else
npcm_fiux_set_direct_rd(fiu);
if (offs + desc->info.offset + len > U32_MAX)
return -EINVAL;
- rpcif_spi_mem_prepare(desc->mem->spi, &desc->info.op_tmpl, &offs, &len);
+ rpcif_spi_mem_prepare(desc->mem->spi, desc->info.op_tmpl, &offs, &len);
return xspi_dirmap_write(rpc->dev, offs, len, buf);
}
if (offs + desc->info.offset + len > U32_MAX)
return -EINVAL;
- rpcif_spi_mem_prepare(desc->mem->spi, &desc->info.op_tmpl, &offs, &len);
+ rpcif_spi_mem_prepare(desc->mem->spi, desc->info.op_tmpl, &offs, &len);
return rpcif_dirmap_read(rpc->dev, offs, len, buf);
}
if (desc->info.offset + desc->info.length > U32_MAX)
return -EINVAL;
- if (!rpcif_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!rpcif_spi_mem_supports_op(desc->mem, desc->info.op_tmpl))
return -EOPNOTSUPP;
if (!rpc->dirmap)
return -EOPNOTSUPP;
- if (!rpc->xspi && desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
+ if (!rpc->xspi && desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
return 0;
{
struct stm32_ospi *ospi = spi_controller_get_devdata(desc->mem->spi->controller);
- if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
+ if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT)
return -EOPNOTSUPP;
/* Should never happen, as mm_base == null is an error probe exit condition */
- if (!ospi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
+ if (!ospi->mm_base && desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
if (!ospi->mm_size)
* spi_mem_op template with offs, len and *buf in order to get
* all needed transfer information into struct spi_mem_op
*/
- memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
+ memcpy(&op, desc->info.op_tmpl, sizeof(struct spi_mem_op));
dev_dbg(ospi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
op.data.nbytes = len;
{
struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller);
- if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
+ if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT)
return -EOPNOTSUPP;
/* should never happen, as mm_base == null is an error probe exit condition */
- if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
+ if (!qspi->mm_base && desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
if (!qspi->mm_size)
* spi_mem_op template with offs, len and *buf in order to get
* all needed transfer information into struct spi_mem_op
*/
- memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
+ memcpy(&op, desc->info.op_tmpl, sizeof(struct spi_mem_op));
dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
op.data.nbytes = len;
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
int cs = spi_get_chipselect(desc->mem->spi, 0);
- if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
+ if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
/*
* direction is directly encoded in the ->op_tmpl.data.dir field.
*/
struct spi_mem_dirmap_info {
- struct spi_mem_op op_tmpl;
+ struct spi_mem_op *op_tmpl;
+ struct spi_mem_op primary_op_tmpl;
u64 offset;
u64 length;
};