arm64: dts: renesas: salvator-common: Describe PCIe/USB3.0 clock generator

Describe the 9FGV0841 PCIe and USB3.0 clock generator present on both
Salvator-X and Salvator-XS boards.  The clock generator supplies 100 MHz
differential clock for both PCIe ports, as well as for the USB 3.0 PHY.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260118135038.8033-8-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index d4a921bed4c3939117ee2f1bfa4572956cba23bd..e505161caa6754412739b1db95654212494f4c44 100644 (file)
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -75,6 +75,12 @@
                enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
        };
 
+       pcie_usb_refclk: clk-x7 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+
        cvbs-in {
                compatible = "composite-video-connector";
                label = "CVBS IN";
@@ -523,6 +529,13 @@
                #gpio-cells = <2>;
        };
 
+       pcie_usb_clk: clk@68 {
+               compatible = "renesas,9fgv0841";
+               reg = <0x68>;
+               clocks = <&pcie_usb_refclk>;
+               #clock-cells = <1>;
+       };
+
        video-receiver@70 {
                compatible = "adi,adv7482";
                reg = <0x70 0x71 0x72 0x73 0x74 0x75
@@ -640,17 +653,27 @@
 };
 
 &pcie_bus_clk {
-       clock-frequency = <100000000>;
+       status = "disabled";
 };
 
 &pciec0 {
+       clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>;
        status = "okay";
 };
 
+&pciec0_rp {
+       clocks = <&pcie_usb_clk 3>;
+};
+
 &pciec1 {
+       clocks = <&cpg CPG_MOD 318>, <&pcie_usb_clk 2>;
        status = "okay";
 };
 
+&pciec1_rp {
+       clocks = <&pcie_usb_clk 4>;
+};
+
 &pfc {
        pinctrl-0 = <&scif_clk_pins>;
        pinctrl-names = "default";
@@ -1038,11 +1061,12 @@
 };
 
 &usb3_phy0 {
+       clocks = <&cpg CPG_MOD 328>, <&pcie_usb_clk 6>, <&usb_extal_clk>;
        status = "okay";
 };
 
 &usb3s0_clk {
-       clock-frequency = <100000000>;
+       status = "disabled";
 };
 
 &vin0 {