arm64: dts: amlogic: s4: fix mmc clock assignment

MMC A and C are mis-represented as having their "clkin0" input connected to
xtal while it is actually connected to the MMC clock, probably in an
attempt to provide 24MHz to the device on this input.

Fix this and assign the clock to 24MHz to actually provide the required
rate.

Fixes: 3ab9d54b5d84 ("arm64: dts: amlogic: enable some device nodes for S4")
Tested-by: Nick Xie <nick@khadas.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260114-amlogic-s4-mmc-fixup-v3-2-a4d3e136b3f2@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index f314f07062abe6f8bb0f540d71659a003cecb661..dfc0a30a6e61be4ece624a6e8f57f4817a4a6055 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -819,13 +819,16 @@
                        reg = <0x0 0xfe088000 0x0 0x800>;
                        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clkc_periphs CLKID_SDEMMC_A>,
-                                <&xtal>,
+                                <&clkc_periphs CLKID_SD_EMMC_A>,
                                 <&clkc_pll CLKID_FCLK_DIV2>;
                        clock-names = "core", "clkin0", "clkin1";
                        resets = <&reset RESET_SD_EMMC_A>;
                        cap-sdio-irq;
                        keep-power-in-suspend;
                        status = "disabled";
+
+                       assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>;
+                       assigned-clock-rates = <24000000>;
                };
 
                sd: mmc@fe08a000 {
@@ -848,13 +851,16 @@
                        reg = <0x0 0xfe08c000 0x0 0x800>;
                        interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
                        clocks = <&clkc_periphs CLKID_NAND>,
-                                <&xtal>,
+                                <&clkc_periphs CLKID_SD_EMMC_C>,
                                 <&clkc_pll CLKID_FCLK_DIV2>;
                        clock-names = "core", "clkin0", "clkin1";
                        resets = <&reset RESET_NAND_EMMC>;
                        no-sdio;
                        no-sd;
                        status = "disabled";
+
+                       assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C>;
+                       assigned-clock-rates = <24000000>;
                };
        };
 };