`docs/internals/s390-opcodes.csv', by grepping for "not implemented".
- FP signalling is not accurate. E.g., the "compare and signal"
instructions behave like their non-signalling counterparts.
-- On machine models predating z10, cachegrind will assume a z10 cache
- architecture. Otherwise, cachegrind will query the hosts cache system
- and use those parameters.
- Some gcc versions use mvc to copy 4/8 byte values. This will affect
certain debug messages. For example, memcheck will complain about
4 one-byte reads/writes instead of just a single read/write.
static const HChar *
s390_irgen_ECAG(UChar r1, UChar r3 __attribute__((unused)), IRTemp op2addr)
{
- if (! s390_host_has_gie) {
- emulation_failure(EmFail_S390X_ecag);
- } else {
- put_gpr_dw0(r1, s390_call_ecag(mkexpr(op2addr)));
- }
+ put_gpr_dw0(r1, s390_call_ecag(mkexpr(op2addr)));
return "ecag";
}
return "Instruction stfle is not supported on this host";
case EmFail_S390X_stckf:
return "Instruction stckf is not supported on this host";
- case EmFail_S390X_ecag:
- return "Instruction ecag is not supported on this host";
case EmFail_S390X_pfpo:
return "Instruction pfpo is not supported on this host";
case EmFail_S390X_DFP_insn:
/* stckf insn is not supported on this host */
EmFail_S390X_stckf,
- /* ecag insn is not supported on this host */
- EmFail_S390X_ecag,
-
/* pfpo insn is not supported on this host */
EmFail_S390X_pfpo,
*LLc = (cache_t) { 262144, 8, 64 };
#elif defined(VGA_s390x)
- //
- // Here is the cache data from older machine models:
- //
- // I1 D1 I/D L2
- // z900 256k/256/4 256k/256/4 16MB
- // z800 256k/256/4 256k/256/4 8MB
- // z990 256k/256/4 256k/256/4 32MB
- // z890 256k/256/4 256k/256/4 32MB
- // z9 256k/256/4 256k/256/4 40MB
- //
- // Sources:
- // (1) IBM System z9 109 Technical Introduction
- // www.redbooks.ibm.com/redbooks/pdfs/sg246669.pdf
- // (2) The microarchitecture of the IBM eServer z900 processor
- // IBM Journal of Research and Development
- // Volume 46, Number 4/5, pp 381-395, July/September 2002
- // (3) The IBM eServer z990 microprocessor
- // IBM Journal of Research and Development
- // Volume 48, Number 3/4, pp 295-309, May/July 2004
- // (4) Charles Webb, IBM
- //
- // L2 data is unfortunately incomplete. Otherwise, we could support
- // machines without the ECAG insn by looking at VEX_S390X_MODEL(hwcaps).
-
- // Default cache configuration is z10-EC (Source: ECAG insn)
- *I1c = (cache_t) { 65536, 4, 256 };
- *D1c = (cache_t) { 131072, 8, 256 };
- *LLc = (cache_t) { 50331648, 24, 256 };
+
+ // Should never get here as the min. required machine model can
+ // query cache information via the ECAG insn.
+ tl_assert(0);
#elif defined(VGA_mips32) || defined(VGA_nanomips)
ci->icaches_maintain_coherence = True;
- if (! (vai->hwcaps & VEX_HWCAPS_S390X_GIE)) {
- // ECAG is not available
- return False;
- }
-
UInt level, cache_kind, info, i;
ULong topology = ecag(0, 0, 0); // get summary
+++ /dev/null
-L1 topology: separate data and instruction; private
-L1 cache line size data: 256
-L1 cache line size insn: 256
-L1 total cachesize data: 131072
-L1 total cachesize insn: 65536
-L1 set. assoc. data: 8
-L1 set. assoc. insn: 4
-L2 topology: unified data and instruction; private
-L2 cache line size data: 256
-L2 cache line size insn: 256
-L2 total cachesize data: 3145728
-L2 total cachesize insn: 3145728
-L2 set. assoc. data: 12
-L2 set. assoc. insn: 12
-L3 topology: unified data and instruction; shared
-L3 cache line size data: 256
-L3 cache line size insn: 256
-L3 total cachesize data: 50331648
-L3 total cachesize insn: 50331648
-L3 set. assoc. data: 24
-L3 set. assoc. insn: 24
-prereq: ../../../tests/s390x_features s390x-genins
prog: ecag