s390_set_facility_bit(addr, S390_FAC_CTREXE, 0);
s390_set_facility_bit(addr, S390_FAC_TREXE, 0);
s390_set_facility_bit(addr, S390_FAC_MSA4, 0);
+ s390_set_facility_bit(addr, S390_FAC_VXE, 0);
+ s390_set_facility_bit(addr, S390_FAC_VXE2, 0);
+ s390_set_facility_bit(addr, S390_FAC_DFLT, 0);
return cc;
}
#define VEX_S390X_MODEL_Z13S 13
#define VEX_S390X_MODEL_Z14 14
#define VEX_S390X_MODEL_Z14_ZR1 15
-#define VEX_S390X_MODEL_UNKNOWN 16 /* always last in list */
+#define VEX_S390X_MODEL_Z15 16
+#define VEX_S390X_MODEL_UNKNOWN 17 /* always last in list */
#define VEX_S390X_MODEL_MASK 0x3F
#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */
#define S390_FAC_TREXE 73 // transactional execution
#define S390_FAC_MSA4 77 // message-security-assist 4
#define S390_FAC_VX 129 // vector facility
+#define S390_FAC_VXE 135 // vector enhancements facility 1
+#define S390_FAC_VXE2 148 // vector enhancements facility 2
+#define S390_FAC_DFLT 151 // deflate-conversion facility
/*--------------------------------------------------------------*/
my %toir_implemented = ();
my %toir_decoded = ();
my %known_arch = map {($_ => 1)}
- qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12);
+ qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12 arch13);
# Patterns for identifying certain extended mnemonics that shall be
# skipped in "s390-opc.txt" and "s390-opcodes.csv".
{ "2965", VEX_S390X_MODEL_Z13S },
{ "3906", VEX_S390X_MODEL_Z14 },
{ "3907", VEX_S390X_MODEL_Z14_ZR1 },
+ { "8561", VEX_S390X_MODEL_Z15 },
+ { "8562", VEX_S390X_MODEL_Z15 },
};
Int model, n, fh;
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
ecag.stdout.exp-z10ec ecag.stdout.exp-z196 ecag.stdout.exp-zec12 \
- ecag.stdout.exp-z13 ecag.stdout.exp-z14 \
+ ecag.stdout.exp-z13 ecag.stdout.exp-z14 ecag.stdout.exp-z15 \
op00.stderr.exp1 op00.stderr.exp2 op00.vgtest \
fixbr.vgtest fixbr.stderr.exp fixbr.stdout.exp \
fpext.vgtest fpext.stderr.exp fpext.stdout.exp \
--- /dev/null
+L1 topology: separate data and instruction; private
+L1 cache line size data: 256
+L1 cache line size insn: 256
+L1 total cachesize data: 131072
+L1 total cachesize insn: 131072
+L1 set. assoc. data: 8
+L1 set. assoc. insn: 8
+L2 topology: separate data and instruction; private
+L2 cache line size data: 256
+L2 cache line size insn: 256
+L2 total cachesize data: 4194304
+L2 total cachesize insn: 4194304
+L2 set. assoc. data: 8
+L2 set. assoc. insn: 8
+L3 topology: unified data and instruction; shared
+L3 cache line size data: 256
+L3 cache line size insn: 256
+L3 total cachesize data: 268435456
+L3 total cachesize insn: 268435456
+L3 set. assoc. data: 32
+L3 set. assoc. insn: 32
+L4 topology: unified data and instruction; shared
+L4 cache line size data: 256
+L4 cache line size insn: 256
+L4 total cachesize data: 1006632960
+L4 total cachesize insn: 1006632960
+L4 set. assoc. data: 60
+L4 set. assoc. insn: 60
{ "2965", "z13s" },
{ "3906", "z14" },
{ "3907", "z14 ZR1"},
+ { "8561", "z15" },
+ { "8562", "z15" },
};