aarch64: Add support for GCS system registers with the +gcs modifier

Given the introduction of system registers associated with the Guarded
Control Stack extension to Armv9.4-a in Binutils and their reliance on
the `+gcs' modifier, we implement the necessary changes in GCC to
allow for them to be recognized by the compiler.

gcc/ChangeLog:

	* config/aarch64/aarch64-option-extensions.def (gcs): New.
	* config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
	(TARGET_THE):  Likewise.
	* doc/invoke.texi (AArch64 Options): Describe GCS.

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 97f03395ffca9526a15c576d9c55aa9b6fdd88a8..02fc895338e716b7bfdcd122aa348e444ac84b6e 100644 (file)
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -163,4 +163,6 @@ AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
 
 AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
 
+AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
+
 #undef AARCH64_OPT_EXTENSION

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index f0af0b43358ef0cf1227c36bfc21f9028bbae7d2..5a776dfdff0ff12891a8ab79a77ebf3fb726e50d 100644 (file)
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -265,6 +265,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
 #define AARCH64_ISA_CSSC          (aarch64_isa_flags & AARCH64_FL_CSSC)
 #define AARCH64_ISA_D128          (aarch64_isa_flags & AARCH64_FL_D128)
 #define AARCH64_ISA_THE                   (aarch64_isa_flags & AARCH64_FL_THE)
+#define AARCH64_ISA_GCS                   (aarch64_isa_flags & AARCH64_FL_GCS)
 
 /* The current function is a normal non-streaming function.  */
 #define TARGET_NON_STREAMING (AARCH64_ISA_SM_OFF)
@@ -465,6 +466,11 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
     enabled through +the.  */
 #define TARGET_THE (AARCH64_ISA_THE)
 
+/*  Armv9.4-A Guarded Control Stack extension system registers are
+    enabled through +gcs.  */
+#define TARGET_GCS (AARCH64_ISA_GCS)
+
+
 /* Standard register usage.  */
 
 /* 31 64-bit general purpose registers R0-R30:

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f5e5546080da18daa3c5045d226448bc4682d068..bff3645eedcf13132a20e0e7b39672d6a282b9bc 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21363,6 +21363,8 @@ Enable the FEAT_SME_F64F64 extension to SME.
 Enable the Scalable Matrix Extension 2.  This also enables SME instructions.
 @item d128
 Enable support for 128-bit system register read/write instructions.
+@item gcs
+Enable support for Armv9.4-a Guarded Control Stack extension.
 @item the
 Enable support for Armv8.9-a/9.4-a translation hardening extension.