]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/dsc: Use helper to calculate range_bpg_offset
authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Fri, 10 Jan 2025 04:41:30 +0000 (10:11 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Fri, 17 Jan 2025 07:17:19 +0000 (12:47 +0530)
We get range_bpg_offset for different bpps based on
linear-interpolation from values given for nearby bpps.
Use a helper to get these values.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250110044131.3162682-2-ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_vdsc.c

index b355c479eda37fd02ef79f29eee9f0c5b9a8b99e..df07090c84eb811acbdcc35461f57bd4e808b62d 100644 (file)
@@ -66,6 +66,13 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
                intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
 }
 
+static int
+get_range_bpg_offset(int bpp_low, int offset_low, int bpp_high, int offset_high, int bpp)
+{
+       return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low),
+                                        (bpp_low - bpp_high));
+}
+
 /*
  * We are using the method provided in DSC 1.2a C-Model in codec_main.c
  * Above method use a common formula to derive values for any combination of DSC
@@ -83,7 +90,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
        int qp_bpc_modifier = (bpc - 8) * 2;
        int uncompressed_bpg_rate;
        int first_line_bpg_offset;
-       u32 res, buf_i, bpp_i;
+       u32 buf_i, bpp_i;
 
        if (vdsc_cfg->slice_height >= 8)
                first_line_bpg_offset =
@@ -163,23 +170,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
                        intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
 
                        /* Calculate range_bpg_offset */
-                       if (bpp <= 8) {
+                       if (bpp <= 8)
                                range_bpg_offset = ofs_und4[buf_i];
-                       } else if (bpp <= 10) {
-                               res = DIV_ROUND_UP(((bpp - 8) *
-                                                   (ofs_und5[buf_i] - ofs_und4[buf_i])), 2);
-                               range_bpg_offset = ofs_und4[buf_i] + res;
-                       } else if (bpp <= 12) {
-                               res = DIV_ROUND_UP(((bpp - 10) *
-                                                   (ofs_und6[buf_i] - ofs_und5[buf_i])), 2);
-                               range_bpg_offset = ofs_und5[buf_i] + res;
-                       } else if (bpp <= 16) {
-                               res = DIV_ROUND_UP(((bpp - 12) *
-                                                   (ofs_und8[buf_i] - ofs_und6[buf_i])), 4);
-                               range_bpg_offset = ofs_und6[buf_i] + res;
-                       } else {
+                       else if (bpp <= 10)
+                               range_bpg_offset = get_range_bpg_offset(8, ofs_und4[buf_i],
+                                                                       10, ofs_und5[buf_i], bpp);
+                       else if (bpp <= 12)
+                               range_bpg_offset = get_range_bpg_offset(10, ofs_und5[buf_i],
+                                                                       12, ofs_und6[buf_i], bpp);
+                       else if (bpp <= 16)
+                               range_bpg_offset = get_range_bpg_offset(12, ofs_und6[buf_i],
+                                                                       16, ofs_und8[buf_i], bpp);
+                       else
                                range_bpg_offset = ofs_und8[buf_i];
-                       }
 
                        vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
                                range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
@@ -215,21 +218,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
                        intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
 
                        /* Calculate range_bpg_offset */
-                       if (bpp <= 6) {
+                       if (bpp <= 6)
                                range_bpg_offset = ofs_und6[buf_i];
-                       } else if (bpp <= 8) {
-                               res = DIV_ROUND_UP(((bpp - 6) *
-                                                   (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
-                               range_bpg_offset = ofs_und6[buf_i] + res;
-                       } else if (bpp <= 12) {
-                               range_bpg_offset = ofs_und8[buf_i];
-                       } else if (bpp <= 15) {
-                               res = DIV_ROUND_UP(((bpp - 12) *
-                                                   (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
-                               range_bpg_offset = ofs_und12[buf_i] + res;
-                       } else {
+                       else if (bpp <= 8)
+                               range_bpg_offset = get_range_bpg_offset(6, ofs_und6[buf_i],
+                                                                       8, ofs_und8[buf_i], bpp);
+                       else if (bpp <= 12)
+                               range_bpg_offset = get_range_bpg_offset(8, ofs_und8[buf_i],
+                                                                       12, ofs_und12[buf_i], bpp);
+                       else if (bpp <= 15)
+                               range_bpg_offset = get_range_bpg_offset(12, ofs_und12[buf_i],
+                                                                       15, ofs_und15[buf_i], bpp);
+                       else
                                range_bpg_offset = ofs_und15[buf_i];
-                       }
 
                        vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
                                range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;