arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks

It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike
the SS0. These gates are part of the TCSR clock controller.

At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR
clock controller for SS1 PHY is disabled on the clk_disable_unused late
initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY
and the SS2 is not used on this device.

This doesn't seem to be a problem on CRD though. It might be that the
RPMh has a vote for it from some other consumer and does not actually
disable it when ther kernel drops its vote.

Either way, these TCSR provided clocks seem to be the correct ones for
the SS1 and SS2, so use them instead.

Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 12099368577627f4c5892905547ed2aec6d69e27..51ad2b2e6375f1642f281c52af048e7ba77c4c25 100644 (file)
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -2940,7 +2940,7 @@
                        reg = <0 0x00fda000 0 0x4000>;
 
                        clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
-                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&tcsr TCSR_USB4_1_CLKREF_EN>,
                                 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
                                 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
                        clock-names = "aux",
@@ -3011,7 +3011,7 @@
                        reg = <0 0x00fdf000 0 0x4000>;
 
                        clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
-                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&tcsr TCSR_USB4_2_CLKREF_EN>,
                                 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
                                 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
                        clock-names = "aux",