clk: renesas: r8a779a0: Add ISP core clocks

Add the ISP core modules clock for Renesas R-Car V3U.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250114183005.2761213-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 4a5b4e2afa92aba8b3d7b567652425bd2b8a3d21..1be7b9592aa62028b47f23429b520c0851f07cb4 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -138,6 +138,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+       DEF_MOD("isp0",          16,    R8A779A0_CLK_S1D1),
+       DEF_MOD("isp1",          17,    R8A779A0_CLK_S1D1),
+       DEF_MOD("isp2",          18,    R8A779A0_CLK_S1D1),
+       DEF_MOD("isp3",          19,    R8A779A0_CLK_S1D1),
        DEF_MOD("avb0",         211,    R8A779A0_CLK_S3D2),
        DEF_MOD("avb1",         212,    R8A779A0_CLK_S3D2),
        DEF_MOD("avb2",         213,    R8A779A0_CLK_S3D2),