phy: lynx-28g: use FIELD_GET() and FIELD_PREP()

Reduce the number of bit field definitions required in this driver (in
the worst case, a read form and a write form), by defining just the
mask, and using the FIELD_GET() and FIELD_PREP() API from
<linux/bitfield.h> with that.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-8-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 219cfeacc5656f15ab9600f9103959abafc0ddd8..439fcd6bdc1c1cfc95da9722bf59862401c531f4 100644 (file)
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /* Copyright (c) 2021-2022 NXP. */
 
+#include <linux/bitfield.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/phy.h>
@@ -29,26 +30,26 @@
 #define PLLnRSTCTL_LOCK(rstctl)                        (((rstctl) & BIT(23)) >> 23)
 
 #define PLLnCR0(pll)                           (0x400 + (pll) * 0x100 + 0x4)
-#define PLLnCR0_REFCLK_SEL(cr0)                        (((cr0) & GENMASK(20, 16)))
+#define PLLnCR0_REFCLK_SEL                     GENMASK(20, 16)
 #define PLLnCR0_REFCLK_SEL_100MHZ              0x0
-#define PLLnCR0_REFCLK_SEL_125MHZ              0x10000
-#define PLLnCR0_REFCLK_SEL_156MHZ              0x20000
-#define PLLnCR0_REFCLK_SEL_150MHZ              0x30000
-#define PLLnCR0_REFCLK_SEL_161MHZ              0x40000
+#define PLLnCR0_REFCLK_SEL_125MHZ              0x1
+#define PLLnCR0_REFCLK_SEL_156MHZ              0x2
+#define PLLnCR0_REFCLK_SEL_150MHZ              0x3
+#define PLLnCR0_REFCLK_SEL_161MHZ              0x4
 
 #define PLLnCR1(pll)                           (0x400 + (pll) * 0x100 + 0x8)
-#define PLLnCR1_FRATE_SEL(cr1)                 (((cr1) & GENMASK(28, 24)))
+#define PLLnCR1_FRATE_SEL                      GENMASK(28, 24)
 #define PLLnCR1_FRATE_5G_10GVCO                        0x0
-#define PLLnCR1_FRATE_5G_25GVCO                        0x10000000
-#define PLLnCR1_FRATE_10G_20GVCO               0x6000000
+#define PLLnCR1_FRATE_5G_25GVCO                        0x10
+#define PLLnCR1_FRATE_10G_20GVCO               0x6
 
 /* Per SerDes lane registers */
 /* Lane a General Control Register */
 #define LNaGCR0(lane)                          (0x800 + (lane) * 0x100 + 0x0)
-#define LNaGCR0_PROTO_SEL_MSK                  GENMASK(7, 3)
-#define LNaGCR0_PROTO_SEL_SGMII                        0x8
-#define LNaGCR0_PROTO_SEL_XFI                  0x50
-#define LNaGCR0_IF_WIDTH_MSK                   GENMASK(2, 0)
+#define LNaGCR0_PROTO_SEL                      GENMASK(7, 3)
+#define LNaGCR0_PROTO_SEL_SGMII                        0x1
+#define LNaGCR0_PROTO_SEL_XFI                  0xa
+#define LNaGCR0_IF_WIDTH                       GENMASK(2, 0)
 #define LNaGCR0_IF_WIDTH_10_BIT                        0x0
 #define LNaGCR0_IF_WIDTH_20_BIT                        0x2
 
@@ -60,13 +61,13 @@
 
 /* Lane a Tx General Control Register */
 #define LNaTGCR0(lane)                         (0x800 + (lane) * 0x100 + 0x24)
+#define LNaTGCR0_USE_PLL                       BIT(28)
 #define LNaTGCR0_USE_PLLF                      0x0
-#define LNaTGCR0_USE_PLLS                      BIT(28)
-#define LNaTGCR0_USE_PLL_MSK                   BIT(28)
+#define LNaTGCR0_USE_PLLS                      0x1
+#define LNaTGCR0_N_RATE                                GENMASK(26, 24)
 #define LNaTGCR0_N_RATE_FULL                   0x0
-#define LNaTGCR0_N_RATE_HALF                   0x1000000
-#define LNaTGCR0_N_RATE_QUARTER                        0x2000000
-#define LNaTGCR0_N_RATE_MSK                    GENMASK(26, 24)
+#define LNaTGCR0_N_RATE_HALF                   0x1
+#define LNaTGCR0_N_RATE_QUARTER                        0x2
 
 #define LNaTECR0(lane)                         (0x800 + (lane) * 0x100 + 0x30)
 
@@ -79,14 +80,13 @@
 
 /* Lane a Rx General Control Register */
 #define LNaRGCR0(lane)                         (0x800 + (lane) * 0x100 + 0x44)
+#define LNaRGCR0_USE_PLL                       BIT(28)
 #define LNaRGCR0_USE_PLLF                      0x0
-#define LNaRGCR0_USE_PLLS                      BIT(28)
-#define LNaRGCR0_USE_PLL_MSK                   BIT(28)
-#define LNaRGCR0_N_RATE_MSK                    GENMASK(26, 24)
+#define LNaRGCR0_USE_PLLS                      0x1
+#define LNaRGCR0_N_RATE                                GENMASK(26, 24)
 #define LNaRGCR0_N_RATE_FULL                   0x0
-#define LNaRGCR0_N_RATE_HALF                   0x1000000
-#define LNaRGCR0_N_RATE_QUARTER                        0x2000000
-#define LNaRGCR0_N_RATE_MSK                    GENMASK(26, 24)
+#define LNaRGCR0_N_RATE_HALF                   0x1
+#define LNaRGCR0_N_RATE_QUARTER                        0x2
 
 #define LNaRGCR1(lane)                         (0x800 + (lane) * 0x100 + 0x48)
 
@@ -97,13 +97,12 @@
 #define LNaRSCCR0(lane)                                (0x800 + (lane) * 0x100 + 0x74)
 
 #define LNaPSS(lane)                           (0x1000 + (lane) * 0x4)
-#define LNaPSS_TYPE(pss)                       (((pss) & GENMASK(30, 24)) >> 24)
+#define LNaPSS_TYPE                            GENMASK(30, 24)
 #define LNaPSS_TYPE_SGMII                      0x4
 #define LNaPSS_TYPE_XFI                                0x28
 
 #define SGMIIaCR1(lane)                                (0x1804 + (lane) * 0x10)
 #define SGMIIaCR1_SGPCS_EN                     BIT(11)
-#define SGMIIaCR1_SGPCS_MSK                    BIT(11)
 
 struct lynx_28g_priv;
 
@@ -197,18 +196,18 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
                                    struct lynx_28g_pll *pll,
                                    phy_interface_t intf)
 {
-       switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+       switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
        case PLLnCR1_FRATE_5G_10GVCO:
        case PLLnCR1_FRATE_5G_25GVCO:
                switch (intf) {
                case PHY_INTERFACE_MODE_SGMII:
                case PHY_INTERFACE_MODE_1000BASEX:
                        lynx_28g_lane_rmw(lane, LNaTGCR0,
-                                         LNaTGCR0_N_RATE_QUARTER,
-                                         LNaTGCR0_N_RATE_MSK);
+                                         FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_QUARTER),
+                                         LNaTGCR0_N_RATE);
                        lynx_28g_lane_rmw(lane, LNaRGCR0,
-                                         LNaRGCR0_N_RATE_QUARTER,
-                                         LNaRGCR0_N_RATE_MSK);
+                                         FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_QUARTER),
+                                         LNaRGCR0_N_RATE);
                        break;
                default:
                        break;
@@ -218,10 +217,12 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
                switch (intf) {
                case PHY_INTERFACE_MODE_10GBASER:
                case PHY_INTERFACE_MODE_USXGMII:
-                       lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_N_RATE_FULL,
-                                         LNaTGCR0_N_RATE_MSK);
-                       lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_N_RATE_FULL,
-                                         LNaRGCR0_N_RATE_MSK);
+                       lynx_28g_lane_rmw(lane, LNaTGCR0,
+                                         FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_FULL),
+                                         LNaTGCR0_N_RATE);
+                       lynx_28g_lane_rmw(lane, LNaRGCR0,
+                                         FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_FULL),
+                                         LNaRGCR0_N_RATE);
                        break;
                default:
                        break;
@@ -236,15 +237,19 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
                                  struct lynx_28g_pll *pll)
 {
        if (pll->id == 0) {
-               lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLF,
-                                 LNaTGCR0_USE_PLL_MSK);
-               lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLF,
-                                 LNaRGCR0_USE_PLL_MSK);
+               lynx_28g_lane_rmw(lane, LNaTGCR0,
+                                 FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLF),
+                                 LNaTGCR0_USE_PLL);
+               lynx_28g_lane_rmw(lane, LNaRGCR0,
+                                 FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLF),
+                                 LNaRGCR0_USE_PLL);
        } else {
-               lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLS,
-                                 LNaTGCR0_USE_PLL_MSK);
-               lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLS,
-                                 LNaRGCR0_USE_PLL_MSK);
+               lynx_28g_lane_rmw(lane, LNaTGCR0,
+                                 FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLS),
+                                 LNaTGCR0_USE_PLL);
+               lynx_28g_lane_rmw(lane, LNaRGCR0,
+                                 FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLS),
+                                 LNaRGCR0_USE_PLL);
        }
 }
 
@@ -286,8 +291,9 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
 
        /* Setup the protocol select and SerDes parallel interface width */
        lynx_28g_lane_rmw(lane, LNaGCR0,
-                         LNaGCR0_PROTO_SEL_SGMII | LNaGCR0_IF_WIDTH_10_BIT,
-                         LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
+                         FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_SGMII) |
+                         FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_10_BIT),
+                         LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
 
        /* Find the PLL that works with this interface type */
        pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
@@ -302,7 +308,7 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
 
        /* Enable the SGMII PCS */
        lynx_28g_lane_rmw(lane, SGMIIaCR1, SGMIIaCR1_SGPCS_EN,
-                         SGMIIaCR1_SGPCS_MSK);
+                         SGMIIaCR1_SGPCS_EN);
 
        /* Configure the appropriate equalization parameters for the protocol */
        iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
@@ -328,8 +334,9 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
 
        /* Setup the protocol select and SerDes parallel interface width */
        lynx_28g_lane_rmw(lane, LNaGCR0,
-                         LNaGCR0_PROTO_SEL_XFI | LNaGCR0_IF_WIDTH_20_BIT,
-                         LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
+                         FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_XFI) |
+                         FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_20_BIT),
+                         LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
 
        /* Find the PLL that works with this interface type */
        pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
@@ -343,7 +350,7 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
        lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
 
        /* Disable the SGMII PCS */
-       lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_MSK);
+       lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
 
        /* Configure the appropriate equalization parameters for the protocol */
        iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
@@ -513,7 +520,7 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
                if (PLLnRSTCTL_DIS(pll->rstctl))
                        continue;
 
-               switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+               switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
                case PLLnCR1_FRATE_5G_10GVCO:
                case PLLnCR1_FRATE_5G_25GVCO:
                        /* 5GHz clock net */
@@ -570,7 +577,7 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
        u32 pss, protocol;
 
        pss = lynx_28g_lane_read(lane, LNaPSS);
-       protocol = LNaPSS_TYPE(pss);
+       protocol = FIELD_GET(LNaPSS_TYPE, pss);
        switch (protocol) {
        case LNaPSS_TYPE_SGMII:
                lane->interface = PHY_INTERFACE_MODE_SGMII;