ASoC: SOF: Intel: lnl: Correct rom_status_reg

[ Upstream commit b852574c671a9983dd51c81582c8c5085f3dc382 ]

ACE2 architecture changed the place where the ROM updates the status code
from the shared SRAM window (and HFFLGP1QW0 in ACE1) to HFDSC register for
the status and HFDEC (HFDSC + 4) for the error code.

The rom_status_reg is not used on LNL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.

Add new header file for lnl specific register definitions.

Fixes: 64a63d9914a5 ("ASoC: SOF: Intel: LNL: Add support for Lunarlake platform")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-4-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/sof/intel/lnl.c b/sound/soc/sof/intel/lnl.c
index 555a51c688dc69db8bedc44d9e1e6f848b1d77ff..d6c4d6cd20b05c07639d8348a853f79bb9b9cc05 100644 (file)
--- a/sound/soc/sof/intel/lnl.c
+++ b/sound/soc/sof/intel/lnl.c
@@ -16,6 +16,7 @@
 #include "hda-ipc.h"
 #include "../sof-audio.h"
 #include "mtl.h"
+#include "lnl.h"
 #include <sound/hda-mlink.h>
 
 /* LunarLake ops */
@@ -176,7 +177,7 @@ const struct sof_intel_dsp_desc lnl_chip_info = {
        .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
        .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
        .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
-       .rom_status_reg = MTL_DSP_ROM_STS,
+       .rom_status_reg = LNL_DSP_REG_HFDSC,
        .rom_init_timeout = 300,
        .ssp_count = MTL_SSP_COUNT,
        .d0i3_offset = MTL_HDA_VS_D0I3C,

diff --git a/sound/soc/sof/intel/lnl.h b/sound/soc/sof/intel/lnl.h
new file mode 100644 (file)
index 0000000..4f4734f
--- /dev/null
+++ b/sound/soc/sof/intel/lnl.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * Copyright(c) 2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __SOF_INTEL_LNL_H
+#define __SOF_INTEL_LNL_H
+
+#define LNL_DSP_REG_HFDSC              0x160200 /* DSP core0 status */
+#define LNL_DSP_REG_HFDEC              0x160204 /* DSP core0 error */
+
+#endif /* __SOF_INTEL_LNL_H */