lwz 3,OFFSET_ppc32_CIA(31)
/* stats only */
- lis 5,VG_(stats__n_xindirs)@ha
- addi 5,5,VG_(stats__n_xindirs)@l
- lwz 6,4(5)
- addic. 6,6,1
- stw 6,4(5)
+ lis 5,VG_(stats__n_xindirs_32)@ha
+ addi 5,5,VG_(stats__n_xindirs_32)@l
lwz 6,0(5)
- addze 6,6
+ addi 6,6,1
stw 6,0(5)
/* r5 = &VG_(tt_fast) */
fast_lookup_failed:
/* stats only */
- lis 5,VG_(stats__n_xindir_misses)@ha
- addi 5,5,VG_(stats__n_xindir_misses)@l
- lwz 6,4(5)
- addic. 6,6,1
- stw 6,4(5)
+ lis 5,VG_(stats__n_xindir_misses_32)@ha
+ addi 5,5,VG_(stats__n_xindir_misses_32)@l
lwz 6,0(5)
- addze 6,6
+ addi 6,6,1
stw 6,0(5)
li 6,VG_TRC_INNER_FASTMISS
.section ".toc","aw"
.tocent__vgPlain_tt_fast:
.tc vgPlain_tt_fast[TC],vgPlain_tt_fast
-.tocent__vgPlain_stats__n_xindirs:
- .tc vgPlain_stats__n_xindirs[TC],vgPlain_stats__n_xindirs
-.tocent__vgPlain_stats__n_xindir_misses:
- .tc vgPlain_stats__n_xindir_misses[TC],vgPlain_stats__n_xindir_misses
+.tocent__vgPlain_stats__n_xindirs_32:
+ .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32
+.tocent__vgPlain_stats__n_xindir_misses_32:
+ .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32
.tocent__vgPlain_machine_ppc64_has_VMX:
.tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX
ld 3,OFFSET_ppc64_CIA(31)
/* stats only */
- ld 5, .tocent__vgPlain_stats__n_xindirs@toc(2)
- ld 6,0(5)
+ ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2)
+ lwz 6,0(5)
addi 6,6,1
- std 6,0(5)
+ stw 6,0(5)
/* r5 = &VG_(tt_fast) */
ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */
.fast_lookup_failed:
/* stats only */
- ld 5, .tocent__vgPlain_stats__n_xindir_misses@toc(2)
- ld 6,0(5)
+ ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2)
+ lwz 6,0(5)
addi 6,6,1
- std 6,0(5)
+ stw 6,0(5)
li 6,VG_TRC_INNER_FASTMISS
li 7,0