clk: at91: clk-sam9x60-pll: fix mul mask

According to datasheet mul mask is on bits 31..24.

Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index e699803986e507da2e7c3eeb978aade19cb7c496..3522eae2edd63cd6c9af4af8fd06a125ddaa3f36 100644 (file)
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -15,7 +15,7 @@
 #include "pmc.h"
 
 #define        PMC_PLL_CTRL0_DIV_MSK   GENMASK(7, 0)
-#define        PMC_PLL_CTRL1_MUL_MSK   GENMASK(30, 24)
+#define        PMC_PLL_CTRL1_MUL_MSK   GENMASK(31, 24)
 
 #define PLL_DIV_MAX            (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
 #define UPLL_DIV               2