drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi

commit 7d5ab3009a8ca777174f6f469277b3922d56fd4b upstream.

May fix display issues with non-HDMI displays.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index cd98c061825029fb5f130a52b8880bacd2ed94b8..927d1703255a5bdb29483e9ac85ca0dd2ac66cfb 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -830,14 +830,16 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
                        args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
                        if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
                                args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
-                       switch (bpc) {
-                       case 8:
-                       default:
-                               args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
-                               break;
-                       case 10:
-                               args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
-                               break;
+                       if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
+                               switch (bpc) {
+                               case 8:
+                               default:
+                                       args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
+                                       break;
+                               case 10:
+                                       args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
+                                       break;
+                               }
                        }
                        args.v5.ucTransmitterID = encoder_id;
                        args.v5.ucEncoderMode = encoder_mode;
@@ -852,20 +854,22 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
                        args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
                        if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
                                args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
-                       switch (bpc) {
-                       case 8:
-                       default:
-                               args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
-                               break;
-                       case 10:
-                               args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
-                               break;
-                       case 12:
-                               args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
-                               break;
-                       case 16:
-                               args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
-                               break;
+                       if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
+                               switch (bpc) {
+                               case 8:
+                               default:
+                                       args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
+                                       break;
+                               case 10:
+                                       args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
+                                       break;
+                               case 12:
+                                       args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
+                                       break;
+                               case 16:
+                                       args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
+                                       break;
+                               }
                        }
                        args.v6.ucTransmitterID = encoder_id;
                        args.v6.ucEncoderMode = encoder_mode;