drm/amd/display: Fix idle check for shared firmware state

[ Upstream commit 3d066f9547dd58329b526db44f42c487a7974703 ]

[WHY]
We still had an instance of get_idle_state checking the PMFW scratch
register instead of the actual idle allow signal.

[HOW]
Replace it with the SW state check for whether we had allowed idle
through notify_idle.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dab26d7e4d52a61fe42ae9405d103078db245f62..b51208f44c240dae0a049bd96c6d7938fb22ff3e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4925,22 +4925,16 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
 
 bool dc_dmub_is_ips_idle_state(struct dc *dc)
 {
-       uint32_t idle_state = 0;
-
        if (dc->debug.disable_idle_power_optimizations)
                return false;
 
        if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
                return false;
 
-       if (dc->hwss.get_idle_state)
-               idle_state = dc->hwss.get_idle_state(dc);
-
-       if (!(idle_state & DMUB_IPS1_ALLOW_MASK) ||
-               !(idle_state & DMUB_IPS2_ALLOW_MASK))
-               return true;
+       if (!dc->ctx->dmub_srv)
+               return false;
 
-       return false;
+       return dc->ctx->dmub_srv->idle_allowed;
 }
 
 /* set min and max memory clock to lowest and highest DPM level, respectively */