dt-bindings: reset: add support for canaan,k230-rst

Introduces a reset controller driver for the Kendryte K230 SoC,
resposible for managing the reset functionality of the CPUs and
various sub-modules.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250613-k230-reset-v4-1-e5266d2be440@pigmoral.tech
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

diff --git a/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
new file mode 100644 (file)
index 0000000..d352d0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/canaan,k230-rst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan Kendryte K230 Reset Controller
+
+maintainers:
+  - Junhui Liu <junhui.liu@pigmoral.tech>
+
+description:
+  The Canaan Kendryte K230 reset controller is part of the SoC's system
+  controller and controls the reset registers for CPUs and various peripherals.
+
+properties:
+  compatible:
+    const: canaan,k230-rst
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@91101000 {
+      compatible = "canaan,k230-rst";
+      reg = <0x91101000 0x1000>;
+      #reset-cells = <1>;
+    };

diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindings/reset/canaan,k230-rst.h
new file mode 100644 (file)
index 0000000..e4f6612
--- /dev/null
+++ b/include/dt-bindings/reset/canaan,k230-rst.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd
+ * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_
+#define _DT_BINDINGS_CANAAN_K230_RST_H_
+
+#define RST_CPU0               0
+#define RST_CPU1               1
+#define RST_CPU0_FLUSH         2
+#define RST_CPU1_FLUSH         3
+#define RST_AI                 4
+#define RST_VPU                        5
+#define RST_HISYS              6
+#define RST_HISYS_AHB          7
+#define RST_SDIO0              8
+#define RST_SDIO1              9
+#define RST_SDIO_AXI           10
+#define RST_USB0               11
+#define RST_USB1               12
+#define RST_USB0_AHB           13
+#define RST_USB1_AHB           14
+#define RST_SPI0               15
+#define RST_SPI1               16
+#define RST_SPI2               17
+#define RST_SEC                        18
+#define RST_PDMA               19
+#define RST_SDMA               20
+#define RST_DECOMPRESS         21
+#define RST_SRAM               22
+#define RST_SHRM_AXIM          23
+#define RST_SHRM_AXIS          24
+#define RST_NONAI2D            25
+#define RST_MCTL               26
+#define RST_ISP                        27
+#define RST_ISP_DW             28
+#define RST_DPU                        29
+#define RST_DISP               30
+#define RST_GPU                        31
+#define RST_AUDIO              32
+#define RST_TIMER0             33
+#define RST_TIMER1             34
+#define RST_TIMER2             35
+#define RST_TIMER3             36
+#define RST_TIMER4             37
+#define RST_TIMER5             38
+#define RST_TIMER_APB          39
+#define RST_HDI                        40
+#define RST_WDT0               41
+#define RST_WDT1               42
+#define RST_WDT0_APB           43
+#define RST_WDT1_APB           44
+#define RST_TS_APB             45
+#define RST_MAILBOX            46
+#define RST_STC                        47
+#define RST_PMU                        48
+#define RST_LOSYS_APB          49
+#define RST_UART0              50
+#define RST_UART1              51
+#define RST_UART2              52
+#define RST_UART3              53
+#define RST_UART4              54
+#define RST_I2C0               55
+#define RST_I2C1               56
+#define RST_I2C2               57
+#define RST_I2C3               58
+#define RST_I2C4               59
+#define RST_JAMLINK0_APB       60
+#define RST_JAMLINK1_APB       61
+#define RST_JAMLINK2_APB       62
+#define RST_JAMLINK3_APB       63
+#define RST_CODEC_APB          64
+#define RST_GPIO_DB            65
+#define RST_GPIO_APB           66
+#define RST_ADC                        67
+#define RST_ADC_APB            68
+#define RST_PWM_APB            69
+#define RST_SHRM_APB           70
+#define RST_CSI0               71
+#define RST_CSI1               72
+#define RST_CSI2               73
+#define RST_CSI_DPHY           74
+#define RST_ISP_AHB            75
+#define RST_M0                 76
+#define RST_M1                 77
+#define RST_M2                 78
+#define RST_SPI2AXI            79
+
+#endif