clk: renesas: r9a09g047: Add WDT clocks and resets

WDT0 reset is for CM33.  Add WDT[1-3] clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 536d922bed703139f081145c653ea30a737c27ab..1886eab9ef9e7e735fc78bd645ac1d0d563d4592 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -92,6 +92,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
        DEF_MOD_CRITICAL("gic_0_gicclk",        CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
                                                BUS_MSTOP(3, BIT(5))),
+       DEF_MOD("wdt_1_clkp",                   CLK_PLLCLN_DIV16, 4, 13, 2, 13,
+                                               BUS_MSTOP(1, BIT(0))),
+       DEF_MOD("wdt_1_clk_loco",               CLK_QEXTAL, 4, 14, 2, 14,
+                                               BUS_MSTOP(1, BIT(0))),
+       DEF_MOD("wdt_2_clkp",                   CLK_PLLCLN_DIV16, 4, 15, 2, 15,
+                                               BUS_MSTOP(5, BIT(12))),
+       DEF_MOD("wdt_2_clk_loco",               CLK_QEXTAL, 5, 0, 2, 16,
+                                               BUS_MSTOP(5, BIT(12))),
+       DEF_MOD("wdt_3_clkp",                   CLK_PLLCLN_DIV16, 5, 1, 2, 17,
+                                               BUS_MSTOP(5, BIT(13))),
+       DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
+                                               BUS_MSTOP(5, BIT(13))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
        DEF_MOD("riic_8_ckm",                   CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -118,6 +130,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(3, 0, 1, 1),            /* SYS_0_PRESETN */
        DEF_RST(3, 8, 1, 9),            /* GIC_0_GICRESET_N */
        DEF_RST(3, 9, 1, 10),           /* GIC_0_DBG_GICRESET_N */
+       DEF_RST(7, 6, 3, 7),            /* WDT_1_RESET */
+       DEF_RST(7, 7, 3, 8),            /* WDT_2_RESET */
+       DEF_RST(7, 8, 3, 9),            /* WDT_3_RESET */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
        DEF_RST(9, 8, 4, 9),            /* RIIC_0_MRST */
        DEF_RST(9, 9, 4, 10),           /* RIIC_1_MRST */