arm64: dts: rockchip: Enable PCIe CLKREQ# for RK3588 on Rock 5b-5bp-5t series

Add supports-clkreq and the corresponding pinmux configurations for PCIe
ASPM L1 substates on the Rock 5B, 5B+ and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware
routing for the CLKREQ# sideband signal is present. This enables support
for PCIe ASPM (Active State Power Management) L1 substates, allowing for
better power efficiency.

Cc: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/20260316073621.39027-1-linux.amoon@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
index b3e76ad2d86940438bf9d58525f1344fe6a9f9eb..bf4a1d2e55ca30b0a4fedcac00a463119a152821 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
@@ -468,7 +468,8 @@
 
 &pcie2x1l0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pcie2_0_rst>;
+       pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>;
+       supports-clkreq;
        reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
        vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
        status = "okay";
@@ -476,7 +477,8 @@
 
 &pcie2x1l2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pcie2_2_rst>;
+       pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>;
+       supports-clkreq;
        reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
        vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
        status = "okay";