arm64: dts: renesas: r9a09g087: Add SPI nodes

Add support for the four SPI controllers on the Renesas RZ/N2H Soc.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251119161434.595677-14-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 361a9235f00d943125352f4f69ee0c351ccad4d1..e273a9aca56871c5ecc82dbc2d64d66d0ae934e3 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -165,6 +165,78 @@
                        status = "disabled";
                };
 
+               rspi0: spi@80007000 {
+                       compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+                       reg = <0x0 0x80007000 0x0 0x400>;
+                       interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "idle", "error", "end", "rx", "tx";
+                       clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+                                <&cpg CPG_MOD 104>;
+                       clock-names = "pclk", "pclkspi";
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               rspi1: spi@80007400 {
+                       compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+                       reg = <0x0 0x80007400 0x0 0x400>;
+                       interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "idle", "error", "end", "rx", "tx";
+                       clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+                                <&cpg CPG_MOD 105>;
+                       clock-names = "pclk", "pclkspi";
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               rspi2: spi@80007800 {
+                       compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+                       reg = <0x0 0x80007800 0x0 0x400>;
+                       interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "idle", "error", "end", "rx", "tx";
+                       clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+                                <&cpg CPG_MOD 106>;
+                       clock-names = "pclk", "pclkspi";
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               rspi3: spi@81007000 {
+                       compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+                       reg = <0x0 0x81007000 0x0 0x400>;
+                       interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "idle", "error", "end", "rx", "tx";
+                       clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+                                <&cpg CPG_MOD 602>;
+                       clock-names = "pclk", "pclkspi";
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                wdt0: watchdog@80082000 {
                        compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
                        reg = <0 0x80082000 0 0x400>,