re PR target/30282 (Optimization flag -O1 -fschedule-insns2 cause red zone to be...

	PR target/30282
	* config/rs6000/rs6000.c (rs6000_emit_stack_reset): Always emit
	blockage for ABI_V4.

From-SVN: r181058

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b94614453e7f6d6f445cf8cb0257cfd14839e25f..506a6a060275b2cf6915615ac13441acf9c9e8e9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-11-07  Alan Modra  <amodra@gmail.com>
+
+       PR target/30282
+       * config/rs6000/rs6000.c (rs6000_emit_stack_reset): Always emit
+       blockage for ABI_V4.
+
 2011-11-04  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR target/50979
@@ -709,7 +715,7 @@
        to flow_loop_nested_p when moving the loop upward.
 
        2011-03-15  Richard Guenther  <rguenther@suse.de>
- 
+
        PR middle-end/48031
        * fold-const.c (fold_indirect_ref_1): Do not create new variable-sized
        or variable-indexed array accesses when in gimple form.
@@ -1933,7 +1939,7 @@
 
        Backport from mainline
        2010-12-06  Jakub Jelinek  <jakub@redhat.com>
- 
+
        PR target/43897
        * config/ia64/ia64.c (rtx_needs_barrier): Handle asm CLOBBER
        as a store into that register.
@@ -3112,7 +3118,7 @@
        Backport from mainline.
        2010-07-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 
-       PR target/43698
+       PR target/43698
        * config/arm/arm.md: Split arm_rev into *arm_rev and *thumb1_rev.
        Set *arm_rev to be predicable.
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 27956c52eb787eb6f56ac411bdcc1f7027083a32..7083584a28eeb7e258a63d991800f17d4d79554d 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -18504,7 +18504,7 @@ rs6000_emit_stack_reset (rs6000_stack_t *info,
 {
   /* This blockage is needed so that sched doesn't decide to move
      the sp change before the register restores.  */
-  if (frame_reg_rtx != sp_reg_rtx
+  if (DEFAULT_ABI == ABI_V4
       || (TARGET_SPE_ABI
          && info->spe_64bit_regs_used != 0
          && info->first_gp_reg_save != 32))