net: phy: dp83867: Always program R/SGMII enable bits

If the board designers have neglected to populate the appropriate
resistors on the strapping pins then the phy may default to the wrong
interface mode. Enable/disable the RGMII/SGMII enable bits as necessary
to select the correct interface.

The dp83867 strapping pins have four levels and typically configure two
features at once. LED_0 controls both port mirroring and whether SGMII
is enabled. If it is pulled to VDDIO, both port mirroring and SGMII
will be enabled. For variants of the dp83867 that do not support SGMII,
this will prevent data from being transferred. As we now explicitly set
the SGMII and RGMII enable bits, we do not need to detect whether SGMII
has been inadvertently enabled.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://patch.msgid.link/20260129171205.3868605-3-sean.anderson@linux.dev
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 7e16e929945799dc21e6b699f20518a02ff370ed..3fb2293f568f02e8fadb485978fa2a3e2018140e 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -75,6 +75,7 @@
 #define MII_DP83867_MICR_JABBER_INT_EN         BIT(0)
 
 /* RGMIICTL bits */
+#define DP83867_RGMII_EN                       BIT(7)
 #define DP83867_RGMII_TX_CLK_DELAY_EN          BIT(1)
 #define DP83867_RGMII_RX_CLK_DELAY_EN          BIT(0)
 
@@ -100,7 +101,7 @@
 #define DP83867_PHYCR_FIFO_DEPTH_MAX           0x03
 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK       GENMASK(15, 14)
 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK       GENMASK(13, 12)
-#define DP83867_PHYCR_RESERVED_MASK            BIT(11)
+#define DP83867_PHYCR_SGMII_EN                 BIT(11)
 #define DP83867_PHYCR_FORCE_LINK_GOOD          BIT(10)
 
 /* RGMIIDCTL bits */
@@ -752,10 +753,12 @@ static int dp83867_config_init(struct phy_device *phydev)
        val |= (dp83867->tx_fifo_depth <<
                DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 
+       val &= ~DP83867_PHYCR_SGMII_EN;
        if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
                val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
                val |= (dp83867->rx_fifo_depth <<
-                       DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
+                       DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) |
+                      DP83867_PHYCR_SGMII_EN;
        }
 
        ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
@@ -763,31 +766,10 @@ static int dp83867_config_init(struct phy_device *phydev)
                return ret;
 
        if (phy_interface_is_rgmii(phydev)) {
-               val = phy_read(phydev, MII_DP83867_PHYCTRL);
-               if (val < 0)
-                       return val;
-
-               /* The code below checks if "port mirroring" N/A MODE4 has been
-                * enabled during power on bootstrap.
-                *
-                * Such N/A mode enabled by mistake can put PHY IC in some
-                * internal testing mode and disable RGMII transmission.
-                *
-                * In this particular case one needs to check STRAP_STS1
-                * register's bit 11 (marked as RESERVED).
-                */
-
-               bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
-               if (bs & DP83867_STRAP_STS1_RESERVED)
-                       val &= ~DP83867_PHYCR_RESERVED_MASK;
-
-               ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
-               if (ret)
-                       return ret;
-
                /* Set up RGMII delays */
                val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 
+               val |= DP83867_RGMII_EN;
                val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
                if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
                        val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
@@ -803,6 +785,10 @@ static int dp83867_config_init(struct phy_device *phydev)
                phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
                              dp83867->rx_id_delay |
                              (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+       } else {
+               val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
+               val &= ~DP83867_RGMII_EN;
+               phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
        }
 
        /* If specified, set io impedance */