]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: s32g: Disable usdhc write-protect
authorCiprian Costea <ciprianmarian.costea@oss.nxp.com>
Thu, 4 Jul 2024 13:56:53 +0000 (16:56 +0300)
committerShawn Guo <shawnguo@kernel.org>
Sun, 11 Aug 2024 12:29:13 +0000 (20:29 +0800)
NXP S32G2/S32G3 SoC based platforms do not
use a pin for SD-Card write protection used by
the uSDHC controller.

Hence, adding 'disable-wp' usdhc device-tree property in order to fix
observed warnings on SD boot as the following:
"host does not support reading read-only switch, assuming write-enable"

Signed-off-by: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts

index 00070c949e2ab2b97ae310ecf660776a0a824cf9..dbe498798bd912a203b037b55d6825c0cc70d4f5 100644 (file)
@@ -34,5 +34,6 @@
 };
 
 &usdhc0 {
+       disable-wp;
        status = "okay";
 };
index b3fc12899cae52971da507f4a71e5fe33116210a..ab1e5caaeae74e6642b31fb54931eb4f76db5507 100644 (file)
@@ -40,5 +40,6 @@
 };
 
 &usdhc0 {
+       disable-wp;
        status = "okay";
 };
index 9d674819876e7f565907c58d042dfc9e38b96264..176e5af191c84ac6cd82ac3d9267723903ad2ea1 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2023 NXP
+ * Copyright 2021-2024 NXP
  *
  * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
  */
@@ -41,5 +41,6 @@
 
 &usdhc0 {
        bus-width = <8>;
+       disable-wp;
        status = "okay";
 };