clk/qcom: qcm2290: Add SDCC1 apps clock frequency table

Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.

Suggested-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20251210155454.1561611-2-loic.poulain@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>

diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
index fad104fb91aec8917de66b63dd546926c8856011..5a599085b500939f74c201229ae9504e4679851f 100644 (file)
--- a/drivers/clk/qcom/clock-qcm2290.c
+++ b/drivers/clk/qcom/clock-qcm2290.c
@@ -17,6 +17,8 @@
 
 #define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608
 #define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c
+#define SDCC1_APPS_CLK_CMD_RCGR 0x38028
+
 
 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625),
@@ -55,6 +57,25 @@ static const struct pll_vote_clk gpll7_clk = {
        .vote_bit = BIT(7),
 };
 
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+       F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
+       F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+       F(20000000, CFG_CLK_SRC_GPLL0_AUX2, 5, 1, 3),
+       F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 1, 2),
+       F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
+       F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
+       F(192000000, CFG_CLK_SRC_GPLL6, 2, 0, 0),
+       F(384000000, CFG_CLK_SRC_GPLL6, 1, 0, 0),
+       {}
+};
+
+static const struct pll_vote_clk gpll6_clk = {
+       .status = 0x6000,
+       .status_bit = BIT(31),
+       .ena_vote = 0x79000,
+       .vote_bit = BIT(7),
+};
+
 static const struct gate_clk qcm2290_clks[] = {
        GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001),
        GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, 0x00000001),
@@ -109,8 +130,12 @@ static ulong qcm2290_set_rate(struct clk *clk, ulong rate)
                                     8);
                return freq->freq;
        case GCC_SDCC1_APPS_CLK:
-               /* The firmware turns this on for us and always sets it to this rate */
-               return 384000000;
+               clk_enable_gpll0(priv->base, &gpll6_clk);
+               freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
+               clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
+                                    freq->pre_div, freq->m, freq->n, freq->src,
+                                    8);
+               return freq->freq;
        default:
                return 0;
        }