RISC-V: Support rounding mode for VFMADD/VFMACC autovec

There will be a case like below for intrinsic and autovec combination

vfadd RTZ   <- intrinisc static rounding
vfmadd      <- autovec/autovec-opt

The autovec generated vfmadd should take DYN mode, and the
frm must be restored before the vfmadd insn. This patch
would like to fix this issue by:

* Add the frm operand to the vfmadd/vfmacc autovec/autovec-opt pattern.
* Set the frm_mode attr to DYN.

Thus, the frm flow when combine autovec and intrinsic should be.

+------------
| frrm  a5
| ...
| fsrmi 4
| vfadd       <- intrinsic static rounding.
| ...
| fsrm  a5
| vfmadd      <- autovec/autovec-opt
| ...
+------------

However, we leverage unspec instead of use to consume the FRM register
because there are some restrictions from the combine pass. Some code
path of try_combine may require the XVECLEN(pat, 0) == 2 for the
recog_for_combine, and add new use will make the XVECLEN(pat, 0) == 3
and result in the vfwmacc optimization failure. For example, in the
test  widen-complicate-5.c and widen-8.c

Finally, there will be other fma cases and they will be covered in
the underlying patches.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc.
	* config/riscv/autovec.md: Ditto.
	* config/riscv/vector-iterators.md: Add UNSPEC_VFFMA.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: New test.

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 899e44b63b56a9831f3661a83561ebf0bf82f358..ccf14f3ea45b6fda0378e9b80684d2f8ec1d89f3 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -459,12 +459,14 @@
 ;; vect__13.182_33 = .FMA (vect__11.180_35, vect__8.176_40, vect__4.172_45);
 (define_insn_and_split "*double_widen_fma<mode>"
   [(set (match_operand:VWEXTF 0 "register_operand")
-       (fma:VWEXTF
-         (float_extend:VWEXTF
-           (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
-         (float_extend:VWEXTF
-           (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
-         (match_operand:VWEXTF 1 "register_operand")))]
+       (unspec:VWEXTF
+         [(fma:VWEXTF
+           (float_extend:VWEXTF
+             (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+           (float_extend:VWEXTF
+             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
+           (match_operand:VWEXTF 1 "register_operand"))
+          (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -475,16 +477,19 @@
     DONE;
   }
   [(set_attr "type" "vfwmuladd")
-   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")
+   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
 
 ;; This helps to match ext + fma.
 (define_insn_and_split "*single_widen_fma<mode>"
   [(set (match_operand:VWEXTF 0 "register_operand")
-       (fma:VWEXTF
-         (float_extend:VWEXTF
-           (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
-         (match_operand:VWEXTF 3 "register_operand")
-         (match_operand:VWEXTF 1 "register_operand")))]
+       (unspec:VWEXTF
+         [(fma:VWEXTF
+           (float_extend:VWEXTF
+             (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+           (match_operand:VWEXTF 3 "register_operand")
+           (match_operand:VWEXTF 1 "register_operand"))
+          (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -501,7 +506,8 @@
     DONE;
   }
   [(set_attr "type" "vfwmuladd")
-   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")
+   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
 
 ;; -------------------------------------------------------------------------
 ;; ---- [FP] VFWNMSAC

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4f6fbf57d301d96ace13cef67e7fc1b628c3f22a..3dded43a42f5a8bc74ef2954368c569baadbd938 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1122,22 +1122,27 @@
 (define_expand "fma<mode>4"
   [(parallel
     [(set (match_operand:VF 0 "register_operand")
-         (fma:VF
-           (match_operand:VF 1 "register_operand")
-           (match_operand:VF 2 "register_operand")
-           (match_operand:VF 3 "register_operand")))
+         (unspec:VF
+           [(fma:VF
+             (match_operand:VF 1 "register_operand")
+             (match_operand:VF 2 "register_operand")
+             (match_operand:VF 3 "register_operand"))
+            (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
      (clobber (match_dup 4))])]
   "TARGET_VECTOR"
   {
     operands[4] = gen_reg_rtx (Pmode);
-  })
+  }
+  [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
 
 (define_insn_and_split "*fma<VF:mode><P:mode>"
   [(set (match_operand:VF 0 "register_operand"   "=vr, vr, ?&vr")
-       (fma:VF
-         (match_operand:VF 1 "register_operand" " %0, vr,   vr")
-         (match_operand:VF 2 "register_operand" " vr, vr,   vr")
-         (match_operand:VF 3 "register_operand" " vr,  0,   vr")))
+       (unspec:VF
+         [(fma:VF
+           (match_operand:VF 1 "register_operand" " %0, vr,   vr")
+           (match_operand:VF 2 "register_operand" " vr, vr,   vr")
+           (match_operand:VF 3 "register_operand" " vr,  0,   vr"))
+          (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
    (clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
   "TARGET_VECTOR"
   "#"
@@ -1151,7 +1156,8 @@
     DONE;
   }
   [(set_attr "type" "vfmuladd")
-   (set_attr "mode" "<VF:MODE>")])
+   (set_attr "mode" "<VF:MODE>")
+   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
 
 ;; -------------------------------------------------------------------------
 ;; ---- [FP] VFNMSAC and VFNMSUB

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 4023a038fe974516e491d4a7bba7f2087513edd6..9b2fb135bddc5fad4f775c0587f2d16d637beca0 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -81,6 +81,8 @@
   UNSPEC_VCOMPRESS
   UNSPEC_VLEFF
   UNSPEC_MODIFY_VL
+
+  UNSPEC_VFFMA
 ])
 
 (define_c_enum "unspecv" [

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
new file mode 100644 (file)
index 0000000..f4f17a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+**test_1:
+**     ...
+**     frrm\t[axt][0-9]+
+**     ...
+**     fsrmi\t1
+**     ...
+**     vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     fsrm\t[axt][0-9]+
+**     ...
+**     vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     ret
+*/
+void
+test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
+       double *in1, double *in2, double *out)
+{
+  *op_out = __riscv_vfsub_vv_f32m1_rm (op1, op2, 1, vl);
+
+  for (int i = 0; i < 4; ++i)
+    out[i] += in1[i] * in2[i];
+}
+
+/*
+**test_2:
+**     ...
+**     frrm\t[axt][0-9]+
+**     ...
+**     fsrmi\t1
+**     ...
+**     vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     fsrm\t[axt][0-9]+
+**     ...
+**     vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     fsrmi\t4
+**     ...
+**     vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     fsrm\t[axt][0-9]+
+**     ...
+**     ret
+*/
+void
+test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
+       double *in1, double *in2, double *out)
+{
+  op2 = __riscv_vfsub_vv_f32m1_rm (op1, op2, 1, vl);
+
+  for (int i = 0; i < 4; ++i)
+    out[i] = out[i] * in1[i] + in2[i];
+
+  *op_out = __riscv_vfsub_vv_f32m1_rm (op1, op2, 4, vl);
+}
+
+/*
+**test_3:
+**     ...
+**     frrm\t[axt][0-9]+
+**     ...
+**     vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     fsrmi\t4
+**     ...
+**     vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+**     ...
+**     fsrm\t[axt][0-9]+
+**     ...
+**     ret
+*/
+void
+test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
+       double *in1, double *in2, double *in3, double *out)
+{
+  for (int i = 0; i < 4; ++i)
+    out[i] = in1[i] + in2[i] * out[i];
+
+  *op_out = __riscv_vfsub_vv_f32m1_rm (op1, op2, 4, vl);
+}