drm/msm/a6xx: Fix PDC sleep sequence

[ Upstream commit f248d5d5159a88ded55329f0b1b463d0f4094228 ]

Since the PDC resides out of the GPU subsystem and cannot be reset in
case it enters bad state, utmost care must be taken to trigger the PDC
wake/sleep routines in the correct order.

The PDC wake sequence can be exercised only after a PDC sleep sequence.
Additionally, GMU firmware should initialize a few registers before the
KMD can trigger a PDC sleep sequence. So PDC sleep can't be done if the
GMU firmware has not initialized. Track these dependencies using a new
status variable and trigger PDC sleep/wake sequences appropriately.

Cc: stable@vger.kernel.org
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673362/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
[ Adjust context ]
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 67fa528f546d331eb58e4ef18f032a0c8741a299..8609fa38058ea056d8e30dab0aa72be4bc2d9c1b 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -236,6 +236,8 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu)
        if (ret)
                DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
 
+       set_bit(GMU_STATUS_FW_START, &gmu->status);
+
        return ret;
 }
 
@@ -482,6 +484,9 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
        int ret;
        u32 val;
 
+       if (!test_and_clear_bit(GMU_STATUS_PDC_SLEEP, &gmu->status))
+               return 0;
+
        gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1));
 
        ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
@@ -509,6 +514,9 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
        int ret;
        u32 val;
 
+       if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status))
+               return;
+
        gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
 
        ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
@@ -517,6 +525,8 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
                DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
 
        gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
+
+       set_bit(GMU_STATUS_PDC_SLEEP, &gmu->status);
 }
 
 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
@@ -645,8 +655,6 @@ setup_pdc:
        /* ensure no writes happen before the uCode is fully written */
        wmb();
 
-       a6xx_rpmh_stop(gmu);
-
 err:
        if (!IS_ERR_OR_NULL(pdcptr))
                iounmap(pdcptr);
@@ -799,19 +807,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
        else
                gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
 
-       if (state == GMU_WARM_BOOT) {
-               ret = a6xx_rpmh_start(gmu);
-               if (ret)
-                       return ret;
-       } else {
+       ret = a6xx_rpmh_start(gmu);
+       if (ret)
+               return ret;
+
+       if (state == GMU_COLD_BOOT) {
                if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
                        "GMU firmware is not loaded\n"))
                        return -ENOENT;
 
-               ret = a6xx_rpmh_start(gmu);
-               if (ret)
-                       return ret;
-
                ret = a6xx_gmu_fw_load(gmu);
                if (ret)
                        return ret;
@@ -980,6 +984,8 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
 
        /* Reset GPU core blocks */
        a6xx_gpu_sw_reset(gpu, true);
+
+       a6xx_rpmh_stop(gmu);
 }
 
 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 94b6c5cab6f435c8965fea8ae5804451c6c3cf29..db5b3b13e7435ae58c47c853bf493da088e336dd 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -99,6 +99,12 @@ struct a6xx_gmu {
        struct completion pd_gate;
 
        struct qmp *qmp;
+
+/* To check if we can trigger sleep seq at PDC. Cleared in a6xx_rpmh_stop() */
+#define GMU_STATUS_FW_START    0
+/* To track if PDC sleep seq was done */
+#define GMU_STATUS_PDC_SLEEP   1
+       unsigned long status;
 };
 
 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)