arm64: dts: socfpga: agilex5: Add L2 and L3 cache

Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 771c594532e76baa1d4850bc24c8e22e8d45ef95..f0379e4eac9d83b0328b7575fe659dd7120996bb 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -37,6 +37,7 @@
                        reg = <0x0>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
 
                cpu1: cpu@1 {
@@ -44,6 +45,7 @@
                        reg = <0x100>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
 
                cpu2: cpu@2 {
@@ -51,6 +53,7 @@
                        reg = <0x200>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
 
                cpu3: cpu@3 {
@@ -58,7 +61,22 @@
                        reg = <0x300>;
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       next-level-cache = <&L3>;
+                       cache-unified;
+               };
+
+               L3: l3-cache {
+                       compatible = "cache";
+                       cache-level = <3>;
+                       cache-unified;
+               };
+
        };
 
        psci {