]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
soc: renesas: r9a09g047-sys: Move common code to a helper
authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Fri, 3 Apr 2026 14:13:39 +0000 (17:13 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 27 Apr 2026 09:27:46 +0000 (11:27 +0200)
Move common code from rzg3e_regmap_{readable,writeable}_reg() to a
helper and use it to avoid code duplication.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260403141341.2851926-4-claudiu.beznea.uj@bp.reneasas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/soc/renesas/r9a09g047-sys.c

index ea3ca10fcc33f8844a8ebd7412cda2feb6154798..b617fb0bde7b8d4703411995f8a26981a55c8152 100644 (file)
@@ -83,11 +83,9 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco
        .print_id = rzg3e_sys_print_id,
 };
 
-static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
+static bool rzg3e_regmap_readable_writeable_reg(unsigned int reg)
 {
        switch (reg) {
-       case SYS_LSI_OTPTSU1TRMVAL0:
-       case SYS_LSI_OTPTSU1TRMVAL1:
        case SYS_SPI_STAADDCS0:
        case SYS_SPI_ENDADDCS0:
        case SYS_SPI_STAADDCS1:
@@ -112,33 +110,25 @@ static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
        }
 }
 
-static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg)
+static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
 {
+       if (rzg3e_regmap_readable_writeable_reg(reg))
+               return true;
+
        switch (reg) {
-       case SYS_SPI_STAADDCS0:
-       case SYS_SPI_ENDADDCS0:
-       case SYS_SPI_STAADDCS1:
-       case SYS_SPI_ENDADDCS1:
-       case SYS_VSP_CLK:
-       case SYS_GBETH0_CFG:
-       case SYS_GBETH1_CFG:
-       case SYS_PCIE_INTX_CH0:
-       case SYS_PCIE_MSI1_CH0:
-       case SYS_PCIE_MSI2_CH0:
-       case SYS_PCIE_MSI3_CH0:
-       case SYS_PCIE_MSI4_CH0:
-       case SYS_PCIE_MSI5_CH0:
-       case SYS_PCIE_PME_CH0:
-       case SYS_PCIE_ACK_CH0:
-       case SYS_PCIE_MISC_CH0:
-       case SYS_PCIE_MODE_CH0:
-       case SYS_ADC_CFG:
+       case SYS_LSI_OTPTSU1TRMVAL0:
+       case SYS_LSI_OTPTSU1TRMVAL1:
                return true;
        default:
                return false;
        }
 }
 
+static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg)
+{
+       return rzg3e_regmap_readable_writeable_reg(reg);
+}
+
 const struct rz_sysc_init_data rzg3e_sys_init_data __initconst = {
        .soc_id_init_data = &rzg3e_sys_soc_id_init_data,
        .readable_reg = rzg3e_regmap_readable_reg,