Updated Link capabilities, Link status and Link capabilities 2 registers decode logic to support PCIe Gen7 speed.
Signed-off-by: Prabu Thangamuthu <prabut@synopsys.com>
return "32GT/s";
case 6:
return "64GT/s";
+ case 8:
+ return "128GT/s";
default:
return "unknown";
}
* highest supported rate.
*/
if (vector & 0x40)
- return "RsvdP";
+ return "2.5-128GT/s";
if (vector & 0x20)
return "2.5-64GT/s";
if (vector & 0x10)
return "32GT/s";
case 6:
return "64GT/s";
+ case 8:
+ return "128GT/s";
default:
return "Unknown";
}