drm/admgpu: Skip CG/PG on SOC21 under SRIOV VF

[ Upstream commit 828418259254863e0af5805bd712284e2bd88e3b ]

[Why]
There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF.
For multi VF, VF should not enable any CG/PG features.
For one VF, PF will program CG/PG related registers.

[How]
Do not set any cg/pg flag bit at early init under sriov.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 8d5c452a910076a844f200ac94796a1e556cc51e..6d3bfb0f03469cc7d7b640da7ce32d58b3174610 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -551,6 +551,10 @@ static int soc21_common_early_init(void *handle)
                        AMD_PG_SUPPORT_JPEG |
                        AMD_PG_SUPPORT_ATHUB |
                        AMD_PG_SUPPORT_MMHUB;
+               if (amdgpu_sriov_vf(adev)) {
+                       adev->cg_flags = 0;
+                       adev->pg_flags = 0;
+               }
                adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
                break;
        case IP_VERSION(11, 0, 2):