]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/i915/dp: Fix AUX IO power enabling for eDP PSR
authorImre Deak <imre.deak@intel.com>
Tue, 10 Sep 2024 11:18:47 +0000 (14:18 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 10 Oct 2024 10:00:03 +0000 (12:00 +0200)
[ Upstream commit ec2231b8dd2dc515912ff7816c420153b4a95e92 ]

Panel Self Refresh on eDP requires the AUX IO power to be enabled
whenever the output (main link) is enabled. This is required by the
AUX_PHY_WAKE/ML_PHY_LOCK signaling initiated by the HW automatically to
re-enable the main link after it got disabled in power saving states
(see eDP v1.4b, sections 5.1, 6.1.3.3.1.1).

The Panel Replay mode on non-eDP outputs on the other hand is only
supported by keeping the main link active, thus not requiring the above
AUX_PHY_WAKE/ML_PHY_LOCK signaling (eDP v1.4b, section 6.1.3.3.1.2).
Thus enabling the AUX IO power for this case is not required either.

Based on the above enable the AUX IO power only for eDP/PSR outputs.

Bspec: 49274, 53370

v2:
- Add a TODO comment to adjust the requirement for AUX IO based on
  whether the ALPM/main-link off mode gets enabled. (Rodrigo)

Cc: Animesh Manna <animesh.manna@intel.com>
Fixes: b8cf5b5d266e ("drm/i915/panelreplay: Initializaton and compute config for panel replay")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910111847.2995725-1-imre.deak@intel.com
(cherry picked from commit f7c2ed9d4ce80a2570c492825de239dc8b500f2e)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/display/intel_psr.h

index 6bff169fa8d4c99e23c053bfe892fdd255007d55..f92c46297ec4ba82d59fce22bf76d030adbb69d4 100644 (file)
@@ -908,7 +908,7 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
         * instead of a specific AUX_IO_<port> reference without powering up any
         * extra wells.
         */
-       if (intel_encoder_can_psr(&dig_port->base))
+       if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state))
                return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
        else if (DISPLAY_VER(i915) < 14 &&
                 (intel_crtc_has_dp_encoder(crtc_state) ||
index 7173ffc7c66c13e9229c046456da46fa4e8b6439..857f776e55509d5d0334c5d96f6df25f9944fe90 100644 (file)
@@ -201,6 +201,25 @@ bool intel_encoder_can_psr(struct intel_encoder *encoder)
                return false;
 }
 
+bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
+                                 const struct intel_crtc_state *crtc_state)
+{
+       /*
+        * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever
+        * the output is enabled. For non-eDP outputs the main link is always
+        * on, hence it doesn't require the HW initiated AUX wake-up signaling used
+        * for eDP.
+        *
+        * TODO:
+        * - Consider leaving AUX IO disabled for eDP / PR as well, in case
+        *   the ALPM with main-link off mode is not enabled.
+        * - Leave AUX IO enabled for DP / PR, once support for ALPM with
+        *   main-link off mode is added for it and this mode gets enabled.
+        */
+       return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+              intel_encoder_can_psr(encoder);
+}
+
 static bool psr_global_enabled(struct intel_dp *intel_dp)
 {
        struct intel_connector *connector = intel_dp->attached_connector;
index d483c85870e1db2e77da54aacc385518aba2eb78..e719f548e1606b959b4524d525eba2a898f138cb 100644 (file)
@@ -25,6 +25,8 @@ struct intel_plane_state;
                                    (intel_dp)->psr.source_panel_replay_support)
 
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
+bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
+                                 const struct intel_crtc_state *crtc_state);
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable_sink(struct intel_dp *intel_dp,
                           const struct intel_crtc_state *crtc_state);