]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema
authorRob Herring (Arm) <robh@kernel.org>
Thu, 10 Jul 2025 18:07:55 +0000 (13:07 -0500)
committerRob Herring (Arm) <robh@kernel.org>
Tue, 15 Jul 2025 04:05:20 +0000 (23:05 -0500)
Convert the Applied Micro X-Gene MSI controller binding to DT schema
format. MSI controllers go in interrupt-controller directory so move the
schema there.

Link: https://lore.kernel.org/r/20250710180757.2970583-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml [new file with mode: 0644]
Documentation/devicetree/bindings/pci/xgene-pci-msi.txt [deleted file]
MAINTAINERS

diff --git a/Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml
new file mode 100644 (file)
index 0000000..49db952
--- /dev/null
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/apm,xgene1-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AppliedMicro X-Gene v1 PCIe MSI controller
+
+maintainers:
+  - Toan Le <toan@os.amperecomputing.com>
+
+properties:
+  compatible:
+    const: apm,xgene1-msi
+
+  msi-controller: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 16
+
+required:
+  - compatible
+  - msi-controller
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    msi@79000000 {
+        compatible = "apm,xgene1-msi";
+        msi-controller;
+        reg = <0x79000000 0x900000>;
+        interrupts = <0x0 0x10 0x4>,
+                     <0x0 0x11 0x4>,
+                     <0x0 0x12 0x4>,
+                     <0x0 0x13 0x4>,
+                     <0x0 0x14 0x4>,
+                     <0x0 0x15 0x4>,
+                     <0x0 0x16 0x4>,
+                     <0x0 0x17 0x4>,
+                     <0x0 0x18 0x4>,
+                     <0x0 0x19 0x4>,
+                     <0x0 0x1a 0x4>,
+                     <0x0 0x1b 0x4>,
+                     <0x0 0x1c 0x4>,
+                     <0x0 0x1d 0x4>,
+                     <0x0 0x1e 0x4>,
+                     <0x0 0x1f 0x4>;
+    };
diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
deleted file mode 100644 (file)
index 85d9b95..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-* AppliedMicro X-Gene v1 PCIe MSI controller
-
-Required properties:
-
-- compatible: should be "apm,xgene1-msi" to identify
-             X-Gene v1 PCIe MSI controller block.
-- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
-- reg: physical base address (0x79000000) and length (0x900000) for controller
-       registers. These registers include the MSI termination address and data
-       registers as well as the MSI interrupt status registers.
-- reg-names: not required
-- interrupts: A list of 16 interrupt outputs of the controller, starting from
-             interrupt number 0x10 to 0x1f.
-- interrupt-names: not required
-
-Each PCIe node needs to have property msi-parent that points to an MSI
-controller node
-
-Examples:
-
-SoC DTSI:
-
-       + MSI node:
-       msi@79000000 {
-               compatible = "apm,xgene1-msi";
-               msi-controller;
-               reg = <0x00 0x79000000 0x0 0x900000>;
-               interrupts =    <0x0 0x10 0x4>
-                               <0x0 0x11 0x4>
-                               <0x0 0x12 0x4>
-                               <0x0 0x13 0x4>
-                               <0x0 0x14 0x4>
-                               <0x0 0x15 0x4>
-                               <0x0 0x16 0x4>
-                               <0x0 0x17 0x4>
-                               <0x0 0x18 0x4>
-                               <0x0 0x19 0x4>
-                               <0x0 0x1a 0x4>
-                               <0x0 0x1b 0x4>
-                               <0x0 0x1c 0x4>
-                               <0x0 0x1d 0x4>
-                               <0x0 0x1e 0x4>
-                               <0x0 0x1f 0x4>;
-       };
-
-       + PCIe controller node with msi-parent property pointing to MSI node:
-       pcie0: pcie@1f2b0000 {
-               device_type = "pci";
-               compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-               reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
-                       0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
-               reg-names = "csr", "cfg";
-               ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
-                         0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
-               dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
-                             0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
-               interrupt-map-mask = <0x0 0x0 0x0 0x7>;
-               interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
-                                0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
-                                0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
-                                0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
-               dma-coherent;
-               clocks = <&pcie0clk 0>;
-               msi-parent= <&msi>;
-       };
index 402da86200c5fb20b262083d004d2ddfedbe04a6..a0d5bc02c7fc16803087b584dbad0ed628735a51 100644 (file)
@@ -19146,7 +19146,7 @@ M:      Toan Le <toan@os.amperecomputing.com>
 L:     linux-pci@vger.kernel.org
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
-F:     Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
+F:     Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml
 F:     drivers/pci/controller/pci-xgene-msi.c
 
 PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS