media: verisilicon: postproc: 4K support

Support input larger than 4096x2048 using extended input width/height
fields of swreg92.
This is needed to decode large WebP or JPEG pictures.

Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>

diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h
index edc217eed293734ddd970766495f944f1a163d69..81328c63b796f30be4736c8f263ce72548ed3a24 100644 (file)
--- a/drivers/media/platform/verisilicon/hantro.h
+++ b/drivers/media/platform/verisilicon/hantro.h
@@ -323,6 +323,8 @@ struct hantro_postproc_regs {
        struct hantro_reg output_fmt;
        struct hantro_reg orig_width;
        struct hantro_reg display_width;
+       struct hantro_reg input_width_ext;
+       struct hantro_reg input_height_ext;
 };
 
 struct hantro_vp9_decoded_buffer_info {

diff --git a/drivers/media/platform/verisilicon/hantro_g1_regs.h b/drivers/media/platform/verisilicon/hantro_g1_regs.h
index c623b3b0be18b99741c1f6fcccc15ef3e7a353b4..7874d76c689851569e564bd7b4640a1fbf22b1eb 100644 (file)
--- a/drivers/media/platform/verisilicon/hantro_g1_regs.h
+++ b/drivers/media/platform/verisilicon/hantro_g1_regs.h
@@ -350,7 +350,7 @@
 #define     G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))
 #define G1_REG_PP_MASK1_ORIG_WIDTH     G1_SWREG(88)
 #define     G1_REG_PP_ORIG_WIDTH(v)    (((v) << 23) & GENMASK(31, 23))
-#define G1_REG_PP_DISPLAY_WIDTH                G1_SWREG(92)
+#define G1_REG_PP_DISPLAY_WIDTH_IN_EXT G1_SWREG(92)
 #define G1_REG_PP_FUSE                 G1_SWREG(99)
 
 #endif /* HANTRO_G1_REGS_H_ */

diff --git a/drivers/media/platform/verisilicon/hantro_postproc.c b/drivers/media/platform/verisilicon/hantro_postproc.c
index 9f559a13d409bb8e6fa916ad15a7553cee26cc95..e94d1ba5ef10b9b64ae7d2ae611aff26bc66b957 100644 (file)
--- a/drivers/media/platform/verisilicon/hantro_postproc.c
+++ b/drivers/media/platform/verisilicon/hantro_postproc.c
@@ -49,7 +49,9 @@ static const struct hantro_postproc_regs hantro_g1_postproc_regs = {
        .input_fmt = {G1_REG_PP_CONTROL, 29, 0x7},
        .output_fmt = {G1_REG_PP_CONTROL, 26, 0x7},
        .orig_width = {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff},
-       .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff},
+       .display_width = {G1_REG_PP_DISPLAY_WIDTH_IN_EXT, 0, 0xfff},
+       .input_width_ext = {G1_REG_PP_DISPLAY_WIDTH_IN_EXT, 26, 0x7},
+       .input_height_ext = {G1_REG_PP_DISPLAY_WIDTH_IN_EXT, 29, 0x7},
 };
 
 bool hantro_needs_postproc(const struct hantro_ctx *ctx,
@@ -103,6 +105,8 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
        HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);
        HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));
        HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
+       HANTRO_PP_REG_WRITE(vpu, input_width_ext, MB_WIDTH(ctx->dst_fmt.width) >> 9);
+       HANTRO_PP_REG_WRITE(vpu, input_height_ext, MB_HEIGHT(ctx->dst_fmt.height >> 8));
 }
 
 static int down_scale_factor(struct hantro_ctx *ctx)