In Cachegrind, allow --cache-sim=no --branch-sim=no. Sometimes just getting

instruction counts is useful.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11382

diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 07d008f1ad9a629ec201d405d39653aa3cd00bc9..690d5d0da5284b0e55b62a1f9acb29783eec7f37 100644 (file)
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -1351,8 +1351,9 @@ static void fprint_CC_table_and_calc_totals(void)
       VG_(sprintf)(buf, "\nevents: Ir "
                                   "Bc Bcm Bi Bim\n");
    }
-   else
-      tl_assert(0); /* can't happen */
+   else {
+      VG_(sprintf)(buf, "\nevents: Ir\n");
+   }
 
    VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
 
@@ -1413,8 +1414,11 @@ static void fprint_CC_table_and_calc_totals(void)
                             lineCC->Bc.b, lineCC->Bc.mp, 
                             lineCC->Bi.b, lineCC->Bi.mp);
       }
-      else
-         tl_assert(0);
+      else {
+         VG_(sprintf)(buf, "%u %llu\n",
+                            lineCC->loc.line,
+                            lineCC->Ir.a);
+      }
 
       VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
 
@@ -1467,8 +1471,11 @@ static void fprint_CC_table_and_calc_totals(void)
                         Bc_total.b, Bc_total.mp, 
                         Bi_total.b, Bi_total.mp);
    }
-   else
-      tl_assert(0);
+   else {
+      VG_(sprintf)(buf, "summary:"
+                        " %llu\n", 
+                        Ir_total.a);
+   }
 
    VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
    VG_(close)(fd);
@@ -1495,10 +1502,6 @@ static void cg_fini(Int exitcode)
          L2_total, L2_total_r, L2_total_w;
    Int l1, l2, l3;
 
-   /* Running with both cache and branch simulation disabled is not
-      allowed (checked during command line option processing). */
-   tl_assert(clo_cache_sim || clo_branch_sim);
-
    fprint_CC_table_and_calc_totals();
 
    if (VG_(clo_verbosity) == 0) 
@@ -1779,14 +1782,6 @@ static void cg_post_clo_init(void)
 {
    cache_t I1c, D1c, L2c; 
 
-   /* Can't disable both cache and branch profiling */
-   if ((!clo_cache_sim) && (!clo_branch_sim)) {
-      VG_(umsg)("ERROR: --cache-sim=no --branch-sim=no is not allowed.\n");
-      VG_(umsg)("You must select cache profiling, "
-                "or branch profiling, or both.\n");
-      VG_(exit)(2);
-   }
-
    CC_table =
       VG_(OSetGen_Create)(offsetof(LineCC, loc),
                           cmp_CodeLoc_LineCC,