/**************************************************************************
*
* These define the EEPROM data structure. They are used in the probe
- * function to verify the existance of the adapter after having sent
+ * function to verify the existence of the adapter after having sent
* the ID_Sequence.
*
* There are others but only the ones we use are defined here.
corkscrew_found_device(int ioaddr, int irq,
int product_index, int options, struct nic *nic)
{
- /* Direct copy from Becker 3c515.c with unecessary parts removed */
+ /* Direct copy from Becker 3c515.c with unnecessary parts removed */
vp->product_name = "3c515";
vp->options = options;
if (options >= 0) {
S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
/*
- * Attempt to get rid of any stray interrupts that occured during
+ * Attempt to get rid of any stray interrupts that occurred during
* configuration. On the i386 this isn't possible because one may
* already be queued. However, a single stray interrupt is
* unimportant.
#define CSTATE 1
#define SSTATE 2
-/* amd8111e decriptor flag definitions */
+/* amd8111e descriptor flag definitions */
typedef enum {
OWN_BIT = (1 << 15),
Fri Nov 22 23:00:00 1996 Markus Gutschke <gutschk@math.uni-muenster.de>
* read the manuals for the CS89x0 chipsets and took note of all the
- changes that will be neccessary in order to adapt Russel Nelson's code
+ changes that will be necessary in order to adapt Russel Nelson's code
to the requirements of a BOOT-Prom
* 6
phy_write_1bit(io_dcr9, PHY_DATA_1);
phy_write_1bit(io_dcr9, PHY_DATA_0);
- /* Send Phy addres */
+ /* Send Phy address */
for (i=0x10; i>0; i=i>>1)
phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
- /* Send register addres */
+ /* Send register address */
for (i=0x10; i>0; i=i>>1)
phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
phy_write_1bit(io_dcr9, PHY_DATA_0);
phy_write_1bit(io_dcr9, PHY_DATA_1);
- /* Send Phy addres */
+ /* Send Phy address */
for (i=0x10; i>0; i=i>>1)
phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
- /* Send register addres */
+ /* Send register address */
for (i=0x10; i>0; i=i>>1)
phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
db->cr0_data = 0;
db->dm910x_chk_mode = 1; /* Enter the check mode */
}
- /* Initilize DM910X board */
+ /* Initialize DM910X board */
dmfe_init_dm910x(nic);
return;
}
-/* Initilize DM910X board
+/* Initialize DM910X board
* Reset DM910X board
- * Initilize TX/Rx descriptor chain structure
+ * Initialize TX/Rx descriptor chain structure
* Send the set-up frame
* Enable Tx/Rx machine
*/
if (!(db->media_mode & DMFE_AUTO))
db->op_mode = db->media_mode; /* Force Mode */
- /* Initiliaze Transmit/Receive decriptor and CR3/4 */
+ /* Initiliaze Transmit/Receive descriptor and CR3/4 */
dmfe_descriptor_init(nic, ioaddr);
/* tx descriptor start pointer */
/*
* Send a setup frame for DM9132
- * This setup frame initilize DM910X addres filter mode
+ * This setup frame initialize DM910X address filter mode
*/
static void dm9132_id_table(struct nic *nic __unused)
/*
* Send a setup frame for DM9102/DM9102A
- * This setup frame initilize DM910X addres filter mode
+ * This setup frame initialize DM910X address filter mode
*/
static void send_filter_frame(struct nic *nic)
phy_write_1bit(ioaddr, PHY_DATA_0);
phy_write_1bit(ioaddr, PHY_DATA_1);
- /* Send Phy addres */
+ /* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr,
phy_addr & i ? PHY_DATA_1 :
PHY_DATA_0);
- /* Send register addres */
+ /* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr,
offset & i ? PHY_DATA_1 :
phy_write_1bit(ioaddr, PHY_DATA_1);
phy_write_1bit(ioaddr, PHY_DATA_0);
- /* Send Phy addres */
+ /* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr,
phy_addr & i ? PHY_DATA_1 :
PHY_DATA_0);
- /* Send register addres */
+ /* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr,
offset & i ? PHY_DATA_1 :
* Initial allocation & initialization of the rx ring.
*
* @v netdev Device of rx ring.
- * @ret rc Non-zero if error occured
+ * @ret rc Non-zero if error occurred
*/
static int ifec_rx_setup ( struct net_device *netdev )
{
outl(tmp, txcon);
- /* Give adress of RX and TX ring to the chip */
+ /* Give address of RX and TX ring to the chip */
outl(virt_to_le32desc(&rx_ring), prcdar);
outl(virt_to_le32desc(&tx_ring), ptcdar);
* Arguments: none
*
* returns: 1 if a packet was received.
- * 0 if no pacet was received.
+ * 0 if no packet was received.
* side effects:
* returns the packet in the array nic->packet.
* returns the length of the packet in nic->packetlen.
#define INTR_RX_STATUS_OK (0x00008000) /* rx status valid. NI */
#define INTR_PCI_TGT_ABT (0x00004000) /* PCI Target abort */
#define INTR_PCI_MASTER_ABT (0x00002000) /* PCI Master abort */
-#define INTR_PCI_PARITY_ERR (0x00001000) /* PCI adress parity error */
+#define INTR_PCI_PARITY_ERR (0x00001000) /* PCI address parity error */
#define INTR_PCI_DATA_ERR (0x00000800) /* PCI data parity error */
#define INTR_RX_THR_CROSSED (0x00000400) /* rx copy threshold crossed */
#define INTR_CNTFULL (0x00000200) /* Counter overflow */
efab_dword_t md_stat;
int count;
- /* wait upto 10ms */
+ /* wait up to 10ms */
for (count = 0; count < 1000; count++) {
falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER );
if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) {
falcon_xmac_writel ( efab, ®, FCN_XX_PWR_RST_REG_MAC );
/* Give some time for the link to establish */
- for (count = 0; count < 1000; count++) { /* wait upto 10ms */
+ for (count = 0; count < 1000; count++) { /* wait up to 10ms */
falcon_xmac_readl ( efab, ®, FCN_XX_PWR_RST_REG_MAC );
if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) {
falcon_setup_xaui ( efab );
falcon_read ( efab, ®, FCN_SRM_CFG_REG_KER );
if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) )
return 0;
- } while (++count < 20); /* wait upto 0.4 sec */
+ } while (++count < 20); /* wait up to 0.4 sec */
EFAB_ERR ( "timed out waiting for SRAM reset\n");
return -ETIMEDOUT;
falcon_write ( efab, ®, FCN_RX_DC_CFG_REG_KER );
/* Set number of RSS CPUs
- * bug7244: Increase filter depth to reduce RX_RESET likelyhood
+ * bug7244: Increase filter depth to reduce RX_RESET likelihood
*/
EFAB_POPULATE_OWORD_5 ( reg,
FCN_NUM_KER, 0,
DBG ( "forcedeth_poll: status = %#04x\n", status );
- /* Link change interrupt occured. Call always if link is down,
+ /* Link change interrupt occurred. Call always if link is down,
* to give auto-neg a chance to finish */
if ( ( status & NVREG_IRQ_LINK ) || ! ( netdev_link_ok ( netdev ) ) )
forcedeth_link_status ( netdev );
return 0;
}
- /* Initilize NonVolatile Storage state. */
+ /* Initialize NonVolatile Storage state. */
priv->nvs.word_len_log2 = 0;
priv->nvs.size = hdr.eeprom_len;
/*================================================================*/
/* Function Declarations */
-/* Frame and header lenght macros */
+/* Frame and header length macros */
#define WLAN_CTL_FRAMELEN(fstype) (\
(fstype) == WLAN_FSTYPE_BLOCKACKREQ ? 24 : \
/*
* On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
* starting until the packet is loaded. Strike one for reliability, lose
- * one for latency - although on PCI this isnt a big loss. Older chips
+ * one for latency - although on PCI this isn't a big loss. Older chips
* have FIFO's smaller than a packet, so you can't do this.
* Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
*/
IntrStatus = 0x20,
IntrMask = 0x24,
IntrControl = 0x28,
- IntrTimer = 0x2c, // unused (Interupt Timer)
+ IntrTimer = 0x2c, // unused (Interrupt Timer)
PMControl = 0x30, // unused (Power Mgmt Control/Status)
rsv2 = 0x34, // reserved
ROMControl = 0x38,
RxSizeMask = 0x0000ffff
/*
* The asic could apparently do vlan, TSO, jumbo (sis191 only) and
- * provide two (unused with Linux) Tx queues. No publically
+ * provide two (unused with Linux) Tx queues. No publicly
* available documentation alas.
*/
};
*
* Side effects:
* leaves the ioaddress of the sis900 chip in the variable ioaddr.
- * leaves the sis900 initialized, and ready to recieve packets.
+ * leaves the sis900 initialized, and ready to receive packets.
*
* Returns: struct nic *: pointer to NIC data structure
*/
mii_status = sis900_mdio_read(phy_addr, MII_STATUS);
if (mii_status == 0xffff || mii_status == 0x0000)
- /* the mii is not accessable, try next one */
+ /* the mii is not accessible, try next one */
continue;
phy_id0 = sis900_mdio_read(phy_addr, MII_PHY_ID0);
/*
Read and write the MII management registers using software-generated
serial MDIO protocol. Note that the command bits and data bits are
- send out seperately
+ sent out separately
*/
static void sis900_mdio_idle(long mdio_addr)
*
* Arguments: struct nic *nic: NIC data structure
*
- * Returns: 1 if a packet was recieved.
- * 0 if no pacet was recieved.
+ * Returns: 1 if a packet was received.
+ * 0 if no packet was received.
*
* Side effects:
* Returns (copies) the packet to the array nic->packet.
PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
- PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
+ PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
- GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
- GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
+ GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
+ GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
- XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
+ XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occurred */
XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
- /* On chips without ram buffer, pause is controled by MAC level */
+ /* On chips without ram buffer, pause is controlled by MAC level */
if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
- PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
+ PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
- GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
- GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
+ GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
+ GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
-#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
+#define RPC_LED_100 (0x05) // LED = 100Mbps link detect
#define RPC_LED_TX (0x06) // LED = TX packet occurred
#define RPC_LED_RX (0x07) // LED = RX packet occurred
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
-#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
+#define RPC_LED_100 (0x05) // LED = 100Mbps link detect
#define RPC_LED_TX (0x06) // LED = TX packet occurred
#define RPC_LED_RX (0x07) // LED = RX packet occurred
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
const char *nic_name;
/* Frequently used values */
- unsigned int cur_rx; /* Producer/consumer ring indicies */
+ unsigned int cur_rx; /* Producer/consumer ring indices */
unsigned int mtu;
/* These values keep track of the tranceiver/media in use */
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
-static int sundance_poll(struct nic *nic, int retreive)
+static int sundance_poll(struct nic *nic, int retrieve)
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
return 0;
/* There is a packet ready */
- if(!retreive)
+ if(!retrieve)
return 1;
intr_status = inw(nic->ioaddr + IntrStatus);
unsigned short vendor_id; /* PCI Vendor code */
unsigned short dev_id; /* PCI Device code */
const char *nic_name;
- unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indicies */
+ unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
unsigned rx_buf_sz; /* Based on mtu + Slack */
struct TLanList *txList;
u32 txHead;
* for this device.
* phy The address of the PHY to be queried.
* reg The register whose contents are to be
-* retreived.
+* retrieved.
* val A pointer to a variable to store the
* retrieved value.
*
-* This function uses the TLAN's MII bus to retreive the contents
+* This function uses the TLAN's MII bus to retrieve the contents
* of a given register on a PHY. It sends the appropriate info
* and then reads the 16-bit register value from the MII bus via
* the TLAN SIO register.
*/
#define EECSR_EEPR 0x80 /* eeprom programed status, 73h means programed */
-#define EECSR_EMBP 0x40 /* eeprom embeded programming */
+#define EECSR_EMBP 0x40 /* eeprom embedded programming */
#define EECSR_AUTOLD 0x20 /* eeprom content reload */
#define EECSR_DPM 0x10 /* eeprom direct programming */
#define EECSR_CS 0x08 /* eeprom CS pin */
* Bits in the CFGA register
*/
-#define CFGA_EELOAD 0x80 /* enable eeprom embeded and direct programming */
+#define CFGA_EELOAD 0x80 /* enable eeprom embedded and direct programming */
#define CFGA_JUMPER 0x40
#define CFGA_MTGPIO 0x08
#define CFGA_T10EN 0x02
static void rhine_init_ring (struct nic *dev);
static void rhine_disable (struct nic *nic);
static void rhine_reset (struct nic *nic);
-static int rhine_poll (struct nic *nic, int retreive);
+static int rhine_poll (struct nic *nic, int retrieve);
static void rhine_transmit (struct nic *nic, const char *d, unsigned int t,
unsigned int s, const char *p);
static void reload_eeprom(int ioaddr);
#define IOSYNC do { inb(nic->ioaddr + StationAddr); } while (0)
static int
-rhine_poll (struct nic *nic, int retreive)
+rhine_poll (struct nic *nic, int retrieve)
{
struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
int rxstatus, good = 0;;
{
unsigned int intr_status;
/* There is a packet ready */
- if(!retreive)
+ if(!retrieve)
return 1;
intr_status = inw(nic->ioaddr + IntrStatus);
/* IP_byte_align[] is used for IP header DWORD byte aligned
0: indicate the IP header won't be DWORD byte aligned.(Default) .
1: indicate the IP header will be DWORD byte aligned.
- In some enviroment, the IP header should be DWORD byte aligned,
+ In some environment, the IP header should be DWORD byte aligned,
or the packet will be droped when we receive it. (eg: IPVS)
*/
VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
* Bits in the EECSR register
*/
-#define EECSR_EMBP 0x40 /* eeprom embeded programming */
+#define EECSR_EMBP 0x40 /* eeprom embedded programming */
#define EECSR_RELOAD 0x20 /* eeprom content reload */
#define EECSR_DPM 0x10 /* eeprom direct programming */
#define EECSR_ECS 0x08 /* eeprom CS pin */
* Linux source.
*/
-/* Virtqueue indicies */
+/* Virtqueue indices */
enum {
RX_INDEX = 0,
TX_INDEX,
/*
* vxge_irq - enable or Disable interrupts
*
- * @netdev netdevice sturcture reference
+ * @netdev netdevice structure reference
* @action requested interrupt action
*/
static void vxge_irq(struct net_device *netdev __unused, int action)
*/
uint8_t data_len[3];
} bytes;
- /** Ths data length (measured in bytes), in network byte
+ /** The data length (measured in bytes), in network byte
* order, with ahs_len as the first byte.
*/
uint32_t ahs_and_data_len;
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
-#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
+#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
}
/* Determine what to do next based on the type of query we
- * issued and the reponse we received
+ * issued and the response we received
*/
switch ( qtype ) {
projects / thirdparty / ipxe.git / commitdiff
