.fast_io = true,
};
-static struct qcom_cc_driver_data gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data gcc_nord_driver_data = {
.dfs_rcgs = gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
};
&gpu_cc_pll0,
};
-static u32 gpu_cc_sm8750_critical_cbcrs[] = {
+static const u32 gpu_cc_sm8750_critical_cbcrs[] = {
0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
0x9008, /* GPU_CC_CXO_AON_CLK */
0x9064, /* GPU_CC_GX_AHB_FF_CLK */
0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */
};
-static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
+static const struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
.alpha_plls = gpu_cc_alpha_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_alpha_plls),
.clk_cbcrs = gpu_cc_sm8750_critical_cbcrs,
qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
}
-static struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
.dfs_rcgs = ne_gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
.clk_regs_configure = clk_nord_regs_configure,
[NW_GCC_VIDEO_BCR] = { 0x1a000 },
};
-static u32 nw_gcc_nord_critical_cbcrs[] = {
+static const u32 nw_gcc_nord_critical_cbcrs[] = {
0x16004, /* NW_GCC_CAMERA_AHB_CLK */
0x16030, /* NW_GCC_CAMERA_XO_CLK */
0x18004, /* NW_GCC_DISP_0_AHB_CLK */
0x1a044, /* NW_GCC_VIDEO_XO_CLK */
};
-static struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
.clk_cbcrs = nw_gcc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(nw_gcc_nord_critical_cbcrs),
};
.fast_io = true,
};
-static struct qcom_cc_driver_data se_gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data se_gcc_nord_driver_data = {
.dfs_rcgs = se_gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks),
};