]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
clk: qcom: Constify qcom_cc_driver_data and list of critical CBCR registers
authorKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Wed, 29 Apr 2026 17:09:00 +0000 (19:09 +0200)
committerBjorn Andersson <andersson@kernel.org>
Sun, 10 May 2026 02:47:04 +0000 (21:47 -0500)
The static 'struct qcom_cc_driver_data' and array 'xxx_critical_cbcrs'
are already treated by common.c code as pointers to const, so constify
few remaining pieces.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429170859.247165-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/gcc-nord.c
drivers/clk/qcom/gpucc-sm8750.c
drivers/clk/qcom/negcc-nord.c
drivers/clk/qcom/nwgcc-nord.c
drivers/clk/qcom/segcc-nord.c

index 3098d8fac0fb2d3515f1d05e8330a7d38dbf0d30..8a6e429f264022d55fc5e59b9ec46ae1124f9ad8 100644 (file)
@@ -1850,7 +1850,7 @@ static const struct regmap_config gcc_nord_regmap_config = {
        .fast_io = true,
 };
 
-static struct qcom_cc_driver_data gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data gcc_nord_driver_data = {
        .dfs_rcgs = gcc_nord_dfs_clocks,
        .num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
 };
index 5d52c6d8b5e51356ee691d8a2ef46e80bffab0cb..1466bd36403f02ffc12d08da8caccae8989660f4 100644 (file)
@@ -421,7 +421,7 @@ static struct clk_alpha_pll *gpu_cc_alpha_plls[] = {
        &gpu_cc_pll0,
 };
 
-static u32 gpu_cc_sm8750_critical_cbcrs[] = {
+static const u32 gpu_cc_sm8750_critical_cbcrs[] = {
        0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
        0x9008, /* GPU_CC_CXO_AON_CLK */
        0x9064, /* GPU_CC_GX_AHB_FF_CLK */
@@ -430,7 +430,7 @@ static u32 gpu_cc_sm8750_critical_cbcrs[] = {
        0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */
 };
 
-static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
+static const struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
        .alpha_plls = gpu_cc_alpha_plls,
        .num_alpha_plls = ARRAY_SIZE(gpu_cc_alpha_plls),
        .clk_cbcrs = gpu_cc_sm8750_critical_cbcrs,
index 1aa24e2784e536e6b6e76f488abd0e2fcc435380..2cb66b0691a65f21e67a4f2d001fe468befacff9 100644 (file)
@@ -1945,7 +1945,7 @@ static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
        qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
 }
 
-static struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
        .dfs_rcgs = ne_gcc_nord_dfs_clocks,
        .num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
        .clk_regs_configure = clk_nord_regs_configure,
index 163ab63c872bc7d5132d68bf0ec3e05f5814974d..961cae47ff7cae22179e0f27bc277e99861ddbc3 100644 (file)
@@ -626,7 +626,7 @@ static const struct qcom_reset_map nw_gcc_nord_resets[] = {
        [NW_GCC_VIDEO_BCR] = { 0x1a000 },
 };
 
-static u32 nw_gcc_nord_critical_cbcrs[] = {
+static const u32 nw_gcc_nord_critical_cbcrs[] = {
        0x16004, /* NW_GCC_CAMERA_AHB_CLK */
        0x16030, /* NW_GCC_CAMERA_XO_CLK */
        0x18004, /* NW_GCC_DISP_0_AHB_CLK */
@@ -641,7 +641,7 @@ static u32 nw_gcc_nord_critical_cbcrs[] = {
        0x1a044, /* NW_GCC_VIDEO_XO_CLK */
 };
 
-static struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
        .clk_cbcrs = nw_gcc_nord_critical_cbcrs,
        .num_clk_cbcrs = ARRAY_SIZE(nw_gcc_nord_critical_cbcrs),
 };
index 1aab0999de4dde7262bd694f7d7f955b2a9cb66e..c82a56d971544f90d30b2467786a76f0f92081ca 100644 (file)
@@ -1568,7 +1568,7 @@ static const struct regmap_config se_gcc_nord_regmap_config = {
        .fast_io = true,
 };
 
-static struct qcom_cc_driver_data se_gcc_nord_driver_data = {
+static const struct qcom_cc_driver_data se_gcc_nord_driver_data = {
        .dfs_rcgs = se_gcc_nord_dfs_clocks,
        .num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks),
 };