arm64: dts: amlogic: gx: assign the MMC signal clocks

The amlogic MMC driver operate with the assumption that MMC clock
is configured to provide 24MHz. It uses this path for low
rates such as 400kHz.

Assign the clocks to make sure they are properly configured

Fixes: 50662499f911 ("ARM64: dts: meson-gx: Use correct mmc clock source 0")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-4-a999fafbe0aa@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index f69923da07febd6b3ebbabd29c848eadca4653a4..a9c830a570cc6cd2875553fa9b0e3ef72a2f6478 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -824,6 +824,9 @@
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
        resets = <&reset RESET_SD_EMMC_A>;
+
+       assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
+       assigned-clock-rates = <24000000>;
 };
 
 &sd_emmc_b {
@@ -832,6 +835,9 @@
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
        resets = <&reset RESET_SD_EMMC_B>;
+
+       assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
+       assigned-clock-rates = <24000000>;
 };
 
 &sd_emmc_c {
@@ -840,6 +846,9 @@
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
        resets = <&reset RESET_SD_EMMC_C>;
+
+       assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
+       assigned-clock-rates = <24000000>;
 };
 
 &simplefb_hdmi {

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index ba535010a3c91d598e72d63fb04243e0c37e9cc9..e202d84f067205fd68fd7953124d77aa19a3704b 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -894,6 +894,9 @@
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
        resets = <&reset RESET_SD_EMMC_A>;
+
+       assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
+       assigned-clock-rates = <24000000>;
 };
 
 &sd_emmc_b {
@@ -902,6 +905,9 @@
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
        resets = <&reset RESET_SD_EMMC_B>;
+
+       assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
+       assigned-clock-rates = <24000000>;
 };
 
 &sd_emmc_c {
@@ -910,6 +916,9 @@
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
        resets = <&reset RESET_SD_EMMC_C>;
+
+       assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
+       assigned-clock-rates = <24000000>;
 };
 
 &simplefb_hdmi {